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From: Thomas Gleixner <tglx@kernel.org>
To: Biju <biju.das.au@gmail.com>, Rob Herring <robh@kernel.org>, Krzysztof
 Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Geert
 Uytterhoeven <geert+renesas@glider.be>, Magnus Damm
 <magnus.damm@gmail.com>
Cc: Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar
 <prabhakar.mahadev-lad.rj@bp.renesas.com>, linux-kernel@vger.kernel.org,
 devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das
 <biju.das.au@gmail.com>
Subject: Re: [PATCH v3 0/9] Add RZ/G3L IRQC support
In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com>
References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com>
Date: Fri, 06 Feb 2026 12:37:49 +0100
Message-ID: <87ecmy14s2.ffs@tglx>
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On Fri, Feb 06 2026 at 11:16, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The IRQC block on RZ/G3L SoC is almost identical to one found on the
> RZ/G3S SoC with the difference like it support more External IRQs, GPT
> Error Interrupts and also has additional registers for GPT/MTU IRQ
> selection, shared IRQ selection between external IRQ and TINT.
>
> It has 16 external interrupts of which 8 interrupts are shared with
> TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
> selection is based on a register in the ICU block.

Can you please give people the time to actually look at your patches
before you repost the full series every other day?