Re: [RFC PATCH 01/10] spi: spi-mem: Introduce support for tuning controller

Santhosh Kumar K
2025-11-05T08:56:08Z

Hello Miquel,

On 28/10/25 21:11, Miquel Raynal wrote:
> Hello Santhosh,
>
> On 20/09/2025 at 23:25:31 +0530, Santhosh Kumar K <s-k6@ti.com> wrote:
>
>> Hello,
>>
>> On 10/09/25 13:51, Miquel Raynal wrote:
>>> On 12/08/2025 at 01:02:10 +0530, Santhosh Kumar K <s-k6@ti.com> wrote:
>>>
>>>> From: Pratyush Yadav <pratyush@kernel.org>
>>>>
>>>> Some controllers like the Cadence OSPI controller need to perform a
>>>> tuning sequence to operate at high data rates. Tuning is needs to happen
>>>> once the device is switched to appropriate mode (say 8S-8S-8S or
>>>> 8D-8D-8D).
>>
>> Apologies for the delay in response - I started prototyping new solution
>> based on our discussions earlier, which took some additional time.
>
> My turn to apologize for the delay, especially since your feedback is
> very complete.
>
>>> This is actually wrong. Tuning is way more generic than that :)
>>> If someone wants to use a chip at a high frequency (50MHz in your
>>> case,
>>> but whatever, there is a threshold above which additional care must be
>>> taken), it must go through the calibration step. It does not matter in
>>> which mode you are. Calibration would still be relevant in single SDR
>>> mode.
>>> This 50MHz bothered Mark because it is too Cadence specific. Maybe
>>> this
>>> should be a controller parameter? If the spi-mem core (or even the spi
>>> core, by extensino) sees that the design allows running at XMHz (due to
>>> the SPI peripheral properties or simply the absence of any limitation),
>>> and if the controller states that it requires an extra tuning step above
>>> YMHz (and X > Y), then it launches the calibration.
>>> From a core perspective, I would like the calibration hook to be as
>>> simple as possible, because what "calibration" means is highly
>>> controller and chip specific.
>>
>> I understand the concern here.
>>
>> Let me point out the options for launching the tuning procedure, along
>> with the issues in each approach.
>
> Very good summary.

Thanks you for the review!

>
>> Option 1: Launch tuning as part of spi_mem_exec_op()
>> - After spi_mem_access_start(), introduce a spi_mem_needs_tuning()
>> check (a new callback to SPI MEM controller) to check whether the
>> current op requires tuning
>> - If yes, we call spi_mem_execute_tuning()
>> - on success, mark tuning complete in a flag within SPI MEM
>> Controller private data
>> - on failure, we attempt a fallback by calling
>> spi_mem_adjust_op_freq() and drop to a lower supported frequency
>>
>> Option 2: Launch tuning within spi_controller->exec_op() implementation
>> - Very similar to option 1, except that the spi_mem_execute_tuning()
>> is triggered from within the controller's exec_op() implementation
>> (no need for spi_mem_needs_tuning())
>>
>> Drawbacks in option 1 and 2:
>> - Tuning requires multiple reads of a known pattern, but the flash
>> may not always be in a state to allow read commands
>> - No fallback on failures, can't make flash-specific adjustments in
>> case of a tuning failure
>> - No access to write_op() to write known pattern temporarily to an
>> on-die cache. Pattern needs to be always burnt into the flash
>>
>> - Plus, in option 2 - we can't call spi_mem_adjust_op_freq()
>
> Two more significant drawbacks:
> - it adds an extra step in the "fast path" -maybe negligible?-
> - spi_mem_exec_op()/->exec_op() are called way before being ready for
> calibration.

Yeah, it's negligible - the tuning runs only the first time that op is
called, and we just store and reuse the parameters after that.

>
>> While the need for tuning is dictated by Controller specific
>> characteristics the ops (and state of the chip) required to complete
>> tuning is under the control of spi-mem users (spi-nand/spi-nor).
>> So, it's impossible to achieve tuning without the help of spi-mem users.
>
> Sounds like a constraint we can afford indeed, especially since the ops
> that can be optimized, are flash specific (relatively few content to
> share between spi nor and spi nand).

True!

>
>> So, Option 3: Launch from SPI MEM clients
>> (mtd/nand/spi or mtd/spi-nor, etc.,)
>> - Once the spi-mem chip is completely enumerated and best read and
>> write ops are chosen call spi_mem_needs_tuning(read_op, write_op) as
>> a part of .probe()
>
> This looks like a decent place, but there is one limitation to
> workaround: picking best read and write ops require knowing what the
> controller is capable of in terms of frequency, which means we must in
> advance expect to set up calibration or not. I don't think it's a
> problem, this is something we know in advance thanks to
> eg. spi-max-frequency in the DT, but I still think a controller specific
> "maximum frequency without calibration" capability must be carried for
> the controller to decide whether this step is needed or not when asked
> by the spi mem client.

Makes sense! We can maintain such a property to directly check whether
tuning is needed or not. I'll add that in.

>
>> - If tuning is required, call
>
> I guess "tuning being required" is a controller choice, based on the
> target frequency for both read/write ops and the controller capability
> to achieve this.
>
>> spi_mem_execute_tuning(read_op, write_op)
>> - If only read_op is provided, it implies the tuning pattern is
>> pre-flashed to the partition
>
> Interesting. I guess that lives some room for tuning PHYs during writes as
> well without more core modifications later, isn't it?

Yeah, you're right. See Patch 08/10 - we enable PHY for data writes.

>
>> - On tuning failure, retry by re-running spi_mem_needs_tuning() with
>> the second best set of ops (max throughput - 1)
>
> I would like to challenge this need. Can the same calibration fail if
> attempted multiple times (eg. because of the heat?) If yes, then we need
> a fallback indeed. Otherwise, I'd be in favor of just failing the
> probe. Calibration is an opt-in -> users must allow a higher frequency
> than they use to in order to enable the feature?

It's possible the same calibration will fail intermittently for
different reasons (temperature changes, as you mentioned). If tuning
fails, the driver should fallback to the non-PHY frequency so the flash
continues operating with slower reads/writes rather than failing the
probe (availability should be prioritized, right?).

>
>> With option 3, spi_mem users are limited to calling
>> spi_mem_needs_tuning() and spi_mem_execute_tuning().
>
> I would even go for a single spi_mem_tune_phy()? Or is there a point in
> having two helpers?

May be not needed, we can do the check and tuning within a single
function.

>
>> Rest is hidden
>> within the controller drivers. If spi-mem users change read/write ops,
>> the above sequence can be re-issued.
>
> I don't have use cases for that in mind, but why not.
>
>> The controller can store the read_op and write_op in case of a tuning
>> success and periodically re-run tuning, ensuring we always have valid
>> tuning parameters.
>
> You'll have to make sure you only use PHY calibration for the ops that
> have been used for the tuning though, because for example as I am
> working on octal DDR support: during S2RAM there may be the need for
> returning to SDR mode, which in turns will have to work without the
> tuning (tuning parameters will be incorrect for this mode for the time
> we run slowly). So either the controller knows which operation should
> enable PHY optimizations, or we must perform the whole calibration again
> every time we suspend (meh).

The controller's calibration logic is straightforward - tuning is
required for higher frequencies and not for lower ones. So we need to
perform calibration each time we switch modes.

In the future, we could enhance this by storing the operations that
require tuning along with their respective calibrated parameters within
the controller.

>
>> One concern with option 3 is that we may not be able to make use of
>> static data on certain flash as tuning patterns (like reading parameter
>> page or SFDP table for tuning instead of controller specific attack
>> patterns).
>
> This is true, I know some devices can send patterns during dummy cycles
> by I have no idea how powerful that is, nor if it can actually be used
> in Linux. One need a controller that is aware of these bits and can
> itself adjust/fine tune its own configuration. For now, I propose to let
> this aside until we get real hardware that can be tested.
>
>> Please let me know your thoughts on which of these directions makes the
>> most sense.
>
> Let's got for option 3. I'm eager to see this moving forward!

Yeah, I'm eager too! I'll send out v2 asap.

Thanks,
Santhosh.

>
> Thanks, Miquèl