From: Andreas Hindborg <a.hindborg@kernel.org>
To: "Boqun Feng" <boqun.feng@gmail.com>
Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org,
lkmm@lists.linux.dev, linux-arch@vger.kernel.org,
"Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <lossin@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Trevor Gross" <tmgross@umich.edu>,
"Danilo Krummrich" <dakr@kernel.org>,
"Will Deacon" <will@kernel.org>,
"Peter Zijlstra" <peterz@infradead.org>,
"Mark Rutland" <mark.rutland@arm.com>,
"Wedson Almeida Filho" <wedsonaf@gmail.com>,
"Viresh Kumar" <viresh.kumar@linaro.org>,
"Lyude Paul" <lyude@redhat.com>, "Ingo Molnar" <mingo@kernel.org>,
"Mitchell Levy" <levymitchell0@gmail.com>,
"Paul E. McKenney" <paulmck@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Linus Torvalds" <torvalds@linux-foundation.org>,
"Thomas Gleixner" <tglx@linutronix.de>
Subject: Re: [PATCH v5 10/10] rust: sync: Add memory barriers
Date: Mon, 30 Jun 2025 11:54:37 +0200 [thread overview]
Message-ID: <87ecv1zh9e.fsf@kernel.org> (raw)
In-Reply-To: <aF9krO0nVjN0yoEC@Mac.home> (Boqun Feng's message of "Fri, 27 Jun 2025 20:42:36 -0700")
"Boqun Feng" <boqun.feng@gmail.com> writes:
> On Thu, Jun 26, 2025 at 03:36:25PM +0200, Andreas Hindborg wrote:
>> "Boqun Feng" <boqun.feng@gmail.com> writes:
> [...]
>> > +//! [`LKMM`]: srctree/tools/memory-mode/
>>
>> Typo in link target.
>>
>> > +
>> > +/// A compiler barrier.
>> > +///
>> > +/// An explicic compiler barrier function that prevents the compiler from moving the memory
>> > +/// accesses either side of it to the other side.
>>
>> Typo in "explicit".
>>
>
> Fixed.
>
>> How about:
>>
>> A compiler barrier. Prevents the compiler from reordering
>> memory access instructions across the barrier.
>>
>>
>> > +pub(crate) fn barrier() {
>> > + // By default, Rust inline asms are treated as being able to access any memory or flags, hence
>> > + // it suffices as a compiler barrier.
>> > + //
>> > + // SAFETY: An empty asm block should be safe.
>> > + unsafe {
>> > + core::arch::asm!("");
>> > + }
>> > +}
>> > +
>> > +/// A full memory barrier.
>> > +///
>> > +/// A barrier function that prevents both the compiler and the CPU from moving the memory accesses
>> > +/// either side of it to the other side.
>>
>>
>> A barrier that prevents compiler and CPU from reordering memory access
>> instructions across the barrier.
>>
>> > +pub fn smp_mb() {
>> > + if cfg!(CONFIG_SMP) {
>> > + // SAFETY: `smp_mb()` is safe to call.
>> > + unsafe {
>> > + bindings::smp_mb();
>> > + }
>> > + } else {
>> > + barrier();
>> > + }
>> > +}
>> > +
>> > +/// A write-write memory barrier.
>> > +///
>> > +/// A barrier function that prevents both the compiler and the CPU from moving the memory write
>> > +/// accesses either side of it to the other side.
>>
>> A barrier that prevents compiler and CPU from reordering memory write
>> instructions across the barrier.
>>
>> > +pub fn smp_wmb() {
>> > + if cfg!(CONFIG_SMP) {
>> > + // SAFETY: `smp_wmb()` is safe to call.
>> > + unsafe {
>> > + bindings::smp_wmb();
>> > + }
>> > + } else {
>> > + barrier();
>> > + }
>> > +}
>> > +
>> > +/// A read-read memory barrier.
>> > +///
>> > +/// A barrier function that prevents both the compiler and the CPU from moving the memory read
>> > +/// accesses either side of it to the other side.
>>
>> A barrier that prevents compiler and CPU from reordering memory read
>> instructions across the barrier.
>>
>
> These are good wording, except that I will use "memory (read/write)
> accesses" instead of "memory (read/write) instructions" because:
>
> 1) "instructions" are at lower level than the language, and memory
> barriers function are provided as synchonization primitives, so I
> feel we should describe memory barrier effects at language level,
> i.e. mention how it would interact with objects and accesses to them.
>
> 2) There are instructions can do read and write in one instruction, it
> might be unclear when we say "prevents reordering an instruction"
> whether both parts are included, for example:
>
> r1 = atomic_add(x, 1); // <- this can be one instruction.
> smp_rmb();
> r2 = atomic_read(y);
>
> people may think because the smp_rmb() prevents read instructions
> reordering, and atomic_add() is one instruction in this case,
> smp_rmb() can prevents the write part of that instruction from
> reordering, but that's not the case.
>
>
> So I will do:
>
> A barrier that prevents compiler and CPU from reordering memory read
> accesses across the barrier.
Right, that makes sense 👍
Best regards,
Andreas Hindborg
next prev parent reply other threads:[~2025-06-30 9:54 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-18 16:49 [PATCH v5 00/10] LKMM generic atomics in Rust Boqun Feng
2025-06-18 16:49 ` [PATCH v5 01/10] rust: Introduce atomic API helpers Boqun Feng
2025-06-26 8:44 ` Andreas Hindborg
2025-06-27 14:00 ` Boqun Feng
2025-06-18 16:49 ` [PATCH v5 02/10] rust: sync: Add basic atomic operation mapping framework Boqun Feng
2025-06-26 8:50 ` Andreas Hindborg
2025-06-26 10:17 ` Andreas Hindborg
2025-06-27 14:30 ` Boqun Feng
2025-06-18 16:49 ` [PATCH v5 03/10] rust: sync: atomic: Add ordering annotation types Boqun Feng
2025-06-19 10:31 ` Peter Zijlstra
2025-06-19 12:19 ` Alice Ryhl
2025-06-19 13:29 ` Boqun Feng
2025-06-19 14:32 ` Peter Zijlstra
2025-06-19 15:00 ` Boqun Feng
2025-06-19 15:10 ` Peter Zijlstra
2025-06-19 15:15 ` Boqun Feng
2025-06-19 18:04 ` Alan Stern
2025-06-21 11:18 ` Gary Guo
2025-06-23 2:48 ` Boqun Feng
2025-06-26 12:36 ` Andreas Hindborg
2025-06-27 14:34 ` Boqun Feng
2025-06-27 14:44 ` Boqun Feng
2025-06-18 16:49 ` [PATCH v5 04/10] rust: sync: atomic: Add generic atomics Boqun Feng
2025-06-21 11:32 ` Gary Guo
2025-06-23 5:19 ` Boqun Feng
2025-06-23 11:54 ` Benno Lossin
2025-06-23 12:58 ` Boqun Feng
2025-06-23 18:30 ` Gary Guo
2025-06-23 19:09 ` Boqun Feng
2025-06-23 23:27 ` Benno Lossin
2025-06-24 16:35 ` Boqun Feng
2025-06-26 13:54 ` Benno Lossin
2025-07-04 21:22 ` Boqun Feng
2025-07-04 22:05 ` Benno Lossin
2025-07-04 22:30 ` Boqun Feng
2025-07-04 22:49 ` Benno Lossin
2025-07-04 23:21 ` Boqun Feng
2025-07-04 20:25 ` Boqun Feng
2025-07-04 20:45 ` Benno Lossin
2025-07-04 21:17 ` Boqun Feng
2025-07-04 22:38 ` Benno Lossin
2025-07-04 23:21 ` Boqun Feng
2025-07-05 8:04 ` Benno Lossin
2025-07-05 15:38 ` Boqun Feng
2025-07-05 21:43 ` Benno Lossin
2025-06-26 12:15 ` Andreas Hindborg
2025-06-27 15:01 ` Boqun Feng
2025-06-30 9:52 ` Andreas Hindborg
2025-06-30 14:44 ` Alan Stern
2025-07-01 8:54 ` Andreas Hindborg
2025-07-01 14:50 ` Boqun Feng
2025-07-02 8:33 ` Andreas Hindborg
2025-06-18 16:49 ` [PATCH v5 05/10] rust: sync: atomic: Add atomic {cmp,}xchg operations Boqun Feng
2025-06-21 11:37 ` Gary Guo
2025-06-23 5:23 ` Boqun Feng
2025-06-26 13:12 ` Andreas Hindborg
2025-06-28 3:03 ` Boqun Feng
2025-06-30 10:16 ` Andreas Hindborg
2025-06-30 14:51 ` Alan Stern
2025-06-30 15:12 ` Boqun Feng
2025-06-27 8:58 ` Benno Lossin
2025-06-27 13:53 ` Boqun Feng
2025-06-28 6:12 ` Benno Lossin
2025-06-28 7:31 ` Boqun Feng
2025-06-28 8:00 ` Benno Lossin
2025-06-30 15:24 ` Boqun Feng
2025-06-30 15:27 ` Boqun Feng
2025-06-30 15:50 ` Benno Lossin
2025-06-18 16:49 ` [PATCH v5 06/10] rust: sync: atomic: Add the framework of arithmetic operations Boqun Feng
2025-06-21 11:41 ` Gary Guo
2025-06-26 12:39 ` Andreas Hindborg
2025-06-28 3:04 ` Boqun Feng
2025-06-18 16:49 ` [PATCH v5 07/10] rust: sync: atomic: Add Atomic<u{32,64}> Boqun Feng
2025-06-26 12:47 ` Andreas Hindborg
2025-06-18 16:49 ` [PATCH v5 08/10] rust: sync: atomic: Add Atomic<{usize,isize}> Boqun Feng
2025-06-26 12:49 ` Andreas Hindborg
2025-06-18 16:49 ` [PATCH v5 09/10] rust: sync: atomic: Add Atomic<*mut T> Boqun Feng
2025-06-18 16:49 ` [PATCH v5 10/10] rust: sync: Add memory barriers Boqun Feng
2025-06-26 13:36 ` Andreas Hindborg
2025-06-28 3:42 ` Boqun Feng
2025-06-30 9:54 ` Andreas Hindborg [this message]
2025-06-18 20:22 ` [PATCH v5 00/10] LKMM generic atomics in Rust Alice Ryhl
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