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From: Thomas Gleixner <tglx@linutronix.de>
To: Marc Zyngier <maz@kernel.org>
Cc: "Raj\, Ashok" <ashok.raj@intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	Alex Williamson <alex.williamson@redhat.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	linux-pci@vger.kernel.org,
	"David S. Miller" <davem@davemloft.net>,
	Kevin Tian <kevin.tian@intel.com>, Ingo Molnar <mingo@kernel.org>,
	x86@kernel.org
Subject: Re: [patch 2/8] PCI/MSI: Mask all unused MSI-X entries
Date: Wed, 28 Jul 2021 12:04:37 +0200	[thread overview]
Message-ID: <87eebi3gay.ffs@nanos.tec.linutronix.de> (raw)
In-Reply-To: <8735s631hq.wl-maz@kernel.org>

On Thu, Jul 22 2021 at 14:46, Marc Zyngier wrote:
> On Wed, 21 Jul 2021 23:57:55 +0100,
> Thomas Gleixner <tglx@linutronix.de> wrote:
>> msix_mask_all() is invoked before the msi descriptors are
>> allocated. msi_desc::masked is actually a misnomer because it's not like
>> the name suggests a boolean representing the masked state. It's caching
>> the content of the PCI_MSIX_ENTRY_VECTOR_CTRL part of the corresponding
>> table entry. Right now this is just using bit 0 (the mask bit), but is
>> that true forever? So we actually should rename that member to
>> vector_ctrl or such.
>
> To follow-up with this forward looking statement, should we only keep
> bit 0 when reading PCI_MSIX_ENTRY_VECTOR_CTRL? I.e.:
>
> 	entry->masked = (readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL) &
> 			 PCI_MSIX_ENTRY_CTRL_MASKBIT);
>
> Or do we want to cache the whole register? In which case I'm all for
> the suggesting renaming (though 'masked' is shared with the old-school
> multi-MSI).

We want to cache the whole register because that's what we need to write
when the mask bit is toggled.

Thanks,

        tglx

  reply	other threads:[~2021-07-28 10:04 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 19:11 [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Thomas Gleixner
2021-07-21 19:11 ` [patch 1/8] PCI/MSI: Enable and mask MSIX early Thomas Gleixner
2021-07-21 21:38   ` Raj, Ashok
2021-07-21 22:51     ` Thomas Gleixner
2021-07-22 21:43   ` Bjorn Helgaas
2021-07-27 20:33     ` Thomas Gleixner
2021-07-21 19:11 ` [patch 2/8] PCI/MSI: Mask all unused MSI-X entries Thomas Gleixner
2021-07-21 22:23   ` Raj, Ashok
2021-07-21 22:57     ` Thomas Gleixner
2021-07-22 13:46       ` Marc Zyngier
2021-07-28 10:04         ` Thomas Gleixner [this message]
2021-07-22 21:45   ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 3/8] PCI/MSI: Enforce that MSI-X table entry is masked for update Thomas Gleixner
2021-07-21 22:32   ` Raj, Ashok
2021-07-21 22:59     ` Thomas Gleixner
2021-07-22 21:46   ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible Thomas Gleixner
2021-07-22 21:48   ` Bjorn Helgaas
     [not found]     ` <CAHp75VdNi4rMuRz8UrW9Haf_Ge8KmNJ0w9ykheqkVhmpXHTUyg@mail.gmail.com>
2021-07-23  8:14       ` Marc Zyngier
2021-07-21 19:11 ` [patch 5/8] PCI/MSI: Simplify msi_verify_entries() Thomas Gleixner
2021-07-21 19:11 ` [patch 6/8] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP Thomas Gleixner
2021-07-22 15:12   ` Marc Zyngier
2021-07-28 10:40     ` Thomas Gleixner
2021-07-21 19:11 ` [patch 7/8] x86/ioapic: Force affinity setup before startup Thomas Gleixner
2021-07-21 19:11 ` [patch 8/8] x86/msi: " Thomas Gleixner
2021-07-21 21:10 ` [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Raj, Ashok
2021-07-21 22:39   ` Thomas Gleixner
2021-07-22 15:17 ` Marc Zyngier
2021-07-22 21:43 ` Bjorn Helgaas
2021-07-27 20:38   ` Thomas Gleixner

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