From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19D6CC433DB for ; Wed, 3 Feb 2021 14:04:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BDEEC64E4E for ; Wed, 3 Feb 2021 14:04:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232575AbhBCODn (ORCPT ); Wed, 3 Feb 2021 09:03:43 -0500 Received: from guitar.tcltek.co.il ([192.115.133.116]:35426 "EHLO mx.tkos.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232448AbhBCOBO (ORCPT ); Wed, 3 Feb 2021 09:01:14 -0500 Received: from tarshish (unknown [10.0.8.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id CF14B440849; Wed, 3 Feb 2021 16:00:31 +0200 (IST) References: <20210203133138.10754-1-kostap@marvell.com> <20210203133138.10754-4-kostap@marvell.com> User-agent: mu4e 1.4.15; emacs 27.1 From: Baruch Siach To: kostap@marvell.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, andrew@lunn.ch, jaz@semihalf.com, gregory.clement@bootlin.com, linux@armlinux.org.uk, nadavh@marvell.com, robh+dt@kernel.org, stefanc@marvell.com, mw@semihalf.com, bpeled@marvell.com, sebastian.hesselbarth@gmail.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce In-reply-to: <20210203133138.10754-4-kostap@marvell.com> Date: Wed, 03 Feb 2021 16:00:31 +0200 Message-ID: <87eehxcku8.fsf@tarshish> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Konstantin, On Wed, Feb 03 2021, kostap@marvell.com wrote: > From: Konstantin Porotchkin > > Add SDIO mode pin control configration for CP0 on A8K DB. This patch does not touch the A8K DB device-tree file. baruch > > Signed-off-by: Konstantin Porotchkin > --- > arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++ > arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++ > 2 files changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi > index 293403a1a333..179218774ba9 100644 > --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi > @@ -47,6 +47,12 @@ > cp0_pinctrl: pinctrl { > compatible = "marvell,armada-7k-pinctrl"; > > + sdhci_pins: sdhi-pins { > + marvell,pins = "mpp56", "mpp57", "mpp58", > + "mpp59", "mpp60", "mpp61", "mpp62"; > + marvell,function = "sdio"; > + }; > + > nand_pins: nand-pins { > marvell,pins = > "mpp15", "mpp16", "mpp17", "mpp18", > diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi > index ee67c70bf02e..64100ae204da 100644 > --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi > @@ -70,6 +70,12 @@ > &cp0_syscon0 { > cp0_pinctrl: pinctrl { > compatible = "marvell,armada-8k-cpm-pinctrl"; > + > + sdhci_pins: sdhi-pins { > + marvell,pins = "mpp56", "mpp57", "mpp58", > + "mpp59", "mpp60", "mpp61", "mpp62"; > + marvell,function = "sdio"; > + }; > }; > }; -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -