From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B1973A1C9 for ; Tue, 31 Mar 2026 14:45:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774968328; cv=none; b=TOMAwM18yW/SbQcyPVu24RN2R/QEWwjrqcszaPRbkjuPNokVNFi3PhX1mYyi0jB8BzDLU0VZkViraCw9v+NeNYvGtFhcsmQDHGNrEj0OJ3A9yHiLJevsCPcJHIcMJ+3HPW3gK/AW4gIp8a649YRKeqTIQz9lPYxaPsLAC7CImAk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774968328; c=relaxed/simple; bh=Y/i10wydnZKhjKyIsNRGfQvLmOoWebzJHa39piewaB8=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=cxpW5AOO+zOkG4oMou+qbPTKT6T11njkWFi1fwlWzm+wO8j+kIf1apugp8jrHyK3wCNYdactFp6OeTNX3FkshvH6uBdSGwOCR3W0+MyRC60oAdX67eodz+34Q0y5fHhsepCom4vmA6Wvx/uZmd3IYpuRyXzy/wZlqFcw3fR06u8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a+gfnqiX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a+gfnqiX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 16C5EC19423; Tue, 31 Mar 2026 14:45:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774968328; bh=Y/i10wydnZKhjKyIsNRGfQvLmOoWebzJHa39piewaB8=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=a+gfnqiXobW80MYXl1W778waxllCiN6OXDIGBSlbAPynOelma6XnD2ozzTTUkgTmI /aewsupCE/LSO21+4FuB09vEF7MWxXkIHbQqNP/o8cQw6egwqvQ1mnqsQvrdhVuPsF Tlf0JXqsBZlJZCT0Um1+lEmQ2iKPrMduJ/yYvegVTQK3nkVFaJeaNzMMYj7khXCnNt Cd73Ar8Jfd6MQebNxf3XBARP8fTh+mFSfHUGhyEagiT5BNV7QJZDDvBNm8tuZ0BB5i /vNr57PuSxoldyCFOyzacmzWITDzdMLaEw1R0VmbskK3TfQcdVtcLgX29TJ2oL1K/g QgC1gDTKe3iKA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Michael Kelley , Dmitry Ilvokhin , Radu Rendec , Jan Kiszka , Kieran Bingham , Florian Fainelli , Marc Zyngier Subject: Re: [patch V4 04/15] x86/irq: Make irqstats array based In-Reply-To: <20260331072418.812332544@kernel.org> References: <20260331071453.172185305@kernel.org> <20260331072418.812332544@kernel.org> Date: Tue, 31 Mar 2026 16:45:24 +0200 Message-ID: <87fr5g9hx7.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, Mar 31 2026 at 09:25, Thomas Gleixner wrote: > +static int __init irq_init_stats(void) > +{ > + struct irq_stat_info *info = irq_stat_info; > + > + for (unsigned int i = 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) { > + if (info->skip_vector && test_bit(info->skip_vector, system_vectors)) > + info->skip_vector = 0; > + } > + > +#ifdef CONFIG_X86_LOCAL_APIC > + if (!x86_platform_ipi_callback) > + irq_stat_info[IRQ_COUNT_X86_PLATFORM_IPI].skip_vector = 1; > +#endif > + > +#ifdef CONFIG_X86_POSTED_MSI > + if (!posted_msi_enabled()) > + irq_stat_info[IRQ_COUNT_POSTED_MSI_NOTIFICATION].skip_vector = 1; > +#endif > + > +#ifdef CONFIG_X86_MCE_AMD > + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && > + boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) > + irq_stat_info[IRQ_COUNT_DEFERRED_VECTOR].skip_vector = 1; Grmbl. IRQ_COUNT_DEFERRED_ERROR. The next patch fixes it but .... > +#endif > + return 0; > +} > +late_initcall(irq_init_stats); > + > +/* > + * Used for default enabled counters to increment the stats and to enable the > + * entry for /proc/interrupts output. > + */ > +void irq_stat_inc_and_enable(enum irq_stat_counts which) > +{ > + this_cpu_inc(irq_stat.counts[which]); > + set_bit(which, irq_stat_count_show); > +} Also this one needs to be in the next patch.