From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9216328F50F; Fri, 30 Jan 2026 14:52:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769784762; cv=none; b=t6XxVaLy770lNMTCGv6ORVRHCefUjhPHfZN147IVwfFn/eYugjcqf8moYt3qlqyyQsjByjirKQxPo7EAQO12FvJT9aKS/MYL+fwtdpWYJ/n0qCkZY/yluPUKY7KXscHygF6TGadkc3B4Wy2Xyd3khOWdCs8iaQdHpATC2yaWoUs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769784762; c=relaxed/simple; bh=KxjC8u30LIXy40FLQVParJ3wLNyEqHVzZGtjgnyIcU4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=aGs87ceZBjLg0QRggHXqGgujNfHyz5rQR8eQQaZhKvZaqMTShgGB7j0JYYoE+F5uzecuBX9JMR+HY8ZQZOygaqM5NHgqWlZ3dlhPaMSZREZ+hzzFja29e45PPOCBD3H2Nidy8OXVnmAtFTVcKApmxdFvburtzhMOuoc0zxnwbTk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PwpN3yb1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PwpN3yb1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A51EBC4CEF7; Fri, 30 Jan 2026 14:52:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769784762; bh=KxjC8u30LIXy40FLQVParJ3wLNyEqHVzZGtjgnyIcU4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=PwpN3yb1zObc/yX7ObOJD36+XQIQYyjsrfp/vQVraMPy2wZYcInjNjh2SMNRI6OrT EgjCAM3rSuREcZMQmN6gk1tV7wcw8GBz4cqnQC2x0Al/srIB/kD5PrcYP2AVcr1e/n +VdNRmnQ3fb0jUfmffjkwajLUq4/0Eptq1nGdYUYR96QImQaLJstwdbXOqBEfTKpDd AN+9Kyuzk2bW7JWHiDzj7eVsGAuMD0p2iYoDu0dbstM12reiIJpefNFD1h11jBstaY qL9tthHOIIHNZsb6n24SXFz0/2A7LjiFZlRnZRyaqFiYCFbzbLJQo6joWLyhuQ1y6H 21q4m0QDNQN8g== From: Thomas Gleixner To: "Lad, Prabhakar" , Geert Uytterhoeven Cc: Philipp Zabel , Magnus Damm , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Subject: Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support In-Reply-To: References: <20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20260121150137.3364865-5-prabhakar.mahadev-lad.rj@bp.renesas.com> <87cy2wcqe2.ffs@tglx> <87bjicm66u.ffs@tglx> Date: Fri, 30 Jan 2026 15:52:38 +0100 Message-ID: <87fr7nkv9l.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Jan 30 2026 at 11:17, Lad, Prabhakar wrote: > On Thu, Jan 29, 2026 at 9:59=E2=80=AFPM Thomas Gleixner = wrote: >> It tries first to inject the interrupt via irq_set_irqchip_state(), >> which only works when a chip in the hierarchy implements the >> chip::irq_set_irqchip_state() callback. >> > I did implement irq_set_irqchip_state but it doesn't land in the > rzv2h_icu_irq_set_irqchip_state(). So I was wondering if I missed > something. > > #Trigger int-ca55-0 > root@rzv2h-evk:/sys/kernel/debug/irq/irqs# echo trigger > 14 > > #The trace looks like below: > irq_debug_write() > -> irq_inject_interrupt() > -> irq_set_irqchip_state() > > This lands in GICV3. For the RZ/V2H ICU only interrupts port_irqx and > tintx interrupts are registered in irq_domain_create_hierarchy() for > the rest of the interrupts these are supposed to be directly handled > by GICv3. ... > How do you propose to handle this? irq_inject_interrupt() would work > if I move int-ca55-x and icu-error-ca55 under > irq_domain_create_hierarchy(). Correct. That's how the hierarchy works.