Re: [PATCH next 2/2] spi: spi-qpic-snand: add support for 8 bits ECC strength

Md Sadre Alam
2025-05-21T05:38:37Z

Hi,

On 5/16/2025 7:44 PM, Miquel Raynal wrote:
>
>>>> Interestingly enough, it reports the correct number of bit errors now.
>>>> For me it seems, that the hardware reports the number of the corrected
>>>> *bytes* instead of the corrected *bits*.
>>> I doubt that, nobody counts bytes of errors.
>>> You results are surprising. I initially though in favour of a software
>>> bug, but then it looks even weirder than that. Alam?
>> I have checked with HW team , the QPIC ECC HW engine reports the bit
>> error byte wise not bit wise.
>>
>> e.g
>> Byte0 --> 2-bitflips --> QPIC ECC counts 1 only
>> Byte1 --> 3-bitflips --> QPIC ECC counts 1 only
>> Byte2 --> 1-bitflips --> QPIC ECC counts 1 only
>> Byte3 --> 4-bitflips --> QPIC ECC counts 1 only (in 8-bit ecc)
>> Byte4 --> 6-bitflips --> QPIC ECC counts 1 only (in 8-bit ecc)
>>
>> Hope this can clearify the things now.
>
> o_O ????
>
> How is that even useful? This basically means UBI will never refresh the
> data because we will constantly underestimate the number of bitflips! We
> need to know the actual number, this averaging does not make any sense
> for Linux. Is there another way to get the raw number of bitflips?
I have re-checked with HW team, unfortunately currently there is no
register fields available to get the raw number of bit flips. But
for newer chipset they have fixed this issue. But currently the QPIC
QPIC_NANDC_BUFFER_STATUS | 0x79B0018 register bit-8 will get set if
there is uncorrectable bitflips happened.

For 4-bit ECC if 5-bit raw bit flips happened then bit-8 will get set in
QPIC_NANDC_BUFFER_STATUS.

similar for 8-bit ECC if 9-bit raw bit flips happened then bit-8 will
get set in QPIC_NANDC_BUFFER_STATUS.

Thanks,
Alam.