From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DEF3231CAB; Tue, 10 Dec 2024 09:06:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733821565; cv=none; b=gTxNJd56GJ+L1dVeUT3JfinoY+2fcUmAX4JlmKhJ9cLz3n0JnwUk5cnWft3BmgxAPgQ47YCr6z+H1d6ciScvipArt1LHHXVqjk0fek4DcBK8pInP3y1tiJ7/jEWFdCVip2wtUe5l+B/ZEoJ8FlBpopCy/XMhKZfW5yxdYP8o/hM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733821565; c=relaxed/simple; bh=UxzPXa/tKxoJipIPRU020pEKj1v70WB+y8JGomD9bMY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=En3rKzZwxULsmtDD3ahtbjZ8EqTQqJBRfLpiwFu092GwuiLgwBNXVWHIEs8RxeDwl6UFqsI+V3FTg5tE3AIjrYraqVigJvLABLuKSkGVoQKzK8Xg1SKAyw8uAVnu/hBw/Hsuf/fouLAW0sh6c7ujkpCMruAQWrWgqrUku/reBVc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J5ADtMND; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J5ADtMND" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CFBD1C4CEDD; Tue, 10 Dec 2024 09:06:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733821564; bh=UxzPXa/tKxoJipIPRU020pEKj1v70WB+y8JGomD9bMY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=J5ADtMNDjrv8Tdc3EOhcbscAr7atYG+YukrITjlrjnZUe4HyauiBujzjNZ1UujMfJ VWwFd4rr8iegccUzExq269wO9mHT/OtKtuHcMcGDdpw7YSIhyAitvYNIXgroTtutW3 CSvd7zFO3bnn5qQE0SrtzQGuelkde7EeBJ733US3Ee6iU4BNzgIhqsLzG5n7+z6a7g unJF6imCcuLorACsmysFxRdFvmjmze0jga2+ZchNVmNrnNpaJHvIE1Y68uvORR63Bm TIpdbMCYMcUHwW+oAduOLEM8ddnSybG4WTa6peRrfTLoA1rYA8Ej752Fqc+WwUkEUY 3APjn6YR47Duw== Received: from 82-132-225-50.dab.02.net ([82.132.225.50] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tKwBu-002CXk-9o; Tue, 10 Dec 2024 09:06:02 +0000 Date: Tue, 10 Dec 2024 09:05:59 +0000 Message-ID: <87frmvsya0.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, ryan.roberts@arm.com, Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: Re: [PATCH V2 46/46] KVM: arm64: nv: Add trap forwarding for FEAT_FGT2 described registers In-Reply-To: <20241210055311.780688-47-anshuman.khandual@arm.com> References: <20241210055311.780688-1-anshuman.khandual@arm.com> <20241210055311.780688-47-anshuman.khandual@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 82.132.225.50 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, ryan.roberts@arm.com, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 10 Dec 2024 05:53:11 +0000, Anshuman Khandual wrote: > > Describe remaining MDCR_EL2 register, and associate that with all FEAT_FGT2 > exposed system registers it allows to trap. MDCR_EL2 register *bits*? How is that related to FGT2 at all? > > Cc: Marc Zyngier > Cc: Oliver Upton > Cc: James Morse > Cc: Suzuki K Poulose > Cc: linux-arm-kernel@lists.infradead.org > Cc: kvmarm@lists.linux.dev > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > Changes in V2: > > - Dropped check_cntr_accessible_N and CGT_CNTR_ACCESSIBLE_N constructs > - SYS_PMEVCNTSVR_EL1(N) access traps have been forwarded to CGT_MDCR_HPMN > - Updated check_mdcr_hpmn() to handle SYS_PMEVCNTSVR_EL1(N) registers > - Changed behaviour as BEHAVE_FORWARD_RW for CGT_MDCR_EnSPM > > arch/arm64/include/asm/kvm_host.h | 2 + > arch/arm64/kvm/emulate-nested.c | 158 ++++++++++++++++++++++++++++++ > 2 files changed, 160 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index c80c07be3358..4cdce62642d1 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -441,6 +441,7 @@ enum vcpu_sysreg { > PMINTENSET_EL1, /* Interrupt Enable Set Register */ > PMOVSSET_EL0, /* Overflow Flag Status Set Register */ > PMUSERENR_EL0, /* User Enable Register */ > + SPMSELR_EL0, /* System PMU Select Register */ How could a system PMU be relevant to a VM? What is the point of bloating the vcpu for something that we will hopefully *never* make visible to guests? > > /* Pointer Authentication Registers in a strict increasing order. */ > APIAKEYLO_EL1, > @@ -501,6 +502,7 @@ enum vcpu_sysreg { > CNTHP_CVAL_EL2, > CNTHV_CTL_EL2, > CNTHV_CVAL_EL2, > + SPMACCESSR_EL2, /* System PMU Access Register */ Same here. It is pretty striking that these registers are never saved/restored or handled as traps, which is a good indication that this is pretty pointless. > > /* Anything from this can be RES0/RES1 sanitised */ > MARKER(__SANITISED_REG_START__), > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > index 6c63cbfc11ea..c7d6d2034f27 100644 > --- a/arch/arm64/kvm/emulate-nested.c > +++ b/arch/arm64/kvm/emulate-nested.c > @@ -79,6 +79,7 @@ enum cgt_group_id { > CGT_MDCR_TDRA, > CGT_MDCR_E2PB, > CGT_MDCR_TPMS, > + CGT_MDCR_EnSPM, > CGT_MDCR_TTRF, > CGT_MDCR_E2TB, > CGT_MDCR_TDCC, > @@ -125,6 +126,7 @@ enum cgt_group_id { > CGT_CNTHCTL_EL1PCTEN = __COMPLEX_CONDITIONS__, > CGT_CNTHCTL_EL1PTEN, > > + CGT_SPMSEL_SPMACCESS, > CGT_CPTR_TTA, > CGT_MDCR_HPMN, > > @@ -351,6 +353,12 @@ static const struct trap_bits coarse_trap_bits[] = { > .mask = MDCR_EL2_TPMS, > .behaviour = BEHAVE_FORWARD_RW, > }, > + [CGT_MDCR_EnSPM] = { > + .index = MDCR_EL2, > + .value = MDCR_EL2_EnSPM, > + .mask = MDCR_EL2_EnSPM, > + .behaviour = BEHAVE_FORWARD_RW, > + }, > [CGT_MDCR_TTRF] = { > .index = MDCR_EL2, > .value = MDCR_EL2_TTRF, > @@ -509,6 +517,7 @@ static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu) > switch (sysreg) { > case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30): > case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30): > + case SYS_PMEVCNTSVR_EL1(0) ... SYS_PMEVCNTSVR_EL1(30): > idx = (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg); > break; > case SYS_PMXEVTYPER_EL0: > @@ -528,6 +537,22 @@ static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu) > return BEHAVE_HANDLE_LOCALLY; > } > > +static enum trap_behaviour check_spmsel_spmaccess(struct kvm_vcpu *vcpu) > +{ > + u64 spmaccessr_el2, spmselr_el2; > + int syspmusel; > + > + if (__vcpu_sys_reg(vcpu, MDCR_EL2) & MDCR_EL2_EnSPM) { I don't mind the test, but I don't see any sanitising of MDCR_EL2 to make EnSPM as RES0 when FEAT_SPMU is not implemented, which will be 100% of the cases. > + spmselr_el2 = __vcpu_sys_reg(vcpu, SPMSELR_EL0); > + spmaccessr_el2 = __vcpu_sys_reg(vcpu, SPMACCESSR_EL2); So these two values are *guaranteed* to be zero. At this stage, what is the point? > + syspmusel = FIELD_GET(SPMSELR_EL0_SYSPMUSEL_MASK, spmselr_el2); > + > + if (((spmaccessr_el2 >> (syspmusel * 2)) & 0x3) == 0x0) > + return BEHAVE_FORWARD_RW; What about value 0b01, which causes *writes* to be trapped? > + } > + return BEHAVE_HANDLE_LOCALLY; And then what? How do we handle this locally? Honestly, short of any additional handling, we would be better off just injecting an UNDEF back into the guest. M. -- Without deviation from the norm, progress is not possible.