From: Marc Zyngier <maz@kernel.org>
To: Jianmin Lv <lvjianmin@loongson.cn>
Cc: Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org, loongarch@lists.linux.dev,
Hanjun Guo <guohanjun@huawei.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@loongson.cn>
Subject: Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
Date: Mon, 18 Jul 2022 07:39:36 +0100 [thread overview]
Message-ID: <87fsiy53h3.wl-maz@kernel.org> (raw)
In-Reply-To: <058aed14-3644-5fc4-8eda-ec645df91836@loongson.cn>
On Mon, 18 Jul 2022 02:07:21 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/17 下午10:49, Marc Zyngier wrote:
> > On Sun, 17 Jul 2022 12:29:05 +0100,
> > Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>
> >>
> >>
> >> On 2022/7/17 下午6:02, Marc Zyngier wrote:
> >>> But the other issue is that you seem to call this function from two
> >>> different locations. This cannot be right, as there should be only one
> >>> probe order, and not multiple.
> >>>
> >>
> >> As we described two IRQ models(Legacy and Extended) in this cover
> >> letter, the parent domain of MSI domain can be htvec domain(Legacy) or
> >> eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
> >> EIOPIC for eiointc) is allowed to pass into kernel, and then in the
> >> irqchip driver, only one kind APIC of them can be parsed from MADT, so
> >> we have to support two probe order for them.
> >
> > Do you really have the two variants in the wild? Or is this just
> > because this is a possibility?
> >
>
> Currently, there are not CPUs(used for PC and server) based on
> LoongArch shipped with only HTPIC, but with both HTPIC and EIOPIC, we
> just want to provide two choices for designers(but obviously, EIOPIC
> may be enough currently). Do you think we don't have to do like this,
> yes? If so, maybe we don't have to support ACPI-way entry for htvec
> currently, and do the work in future if required.
If the existing HW is only following the 'Extended' model, then I'd
suggest you only support this for now. It has two effects:
- it simplifies the current code, making it more maintainable and
easier to reason about
- it sends the message to integrators that 'Extended' is the correct
model, and that it is what they should support
Now, we don't have much time left to get this series into -next (I
will be closing the tree to new features this week, and only queue
fixes).
So whatever you need to do, please do it quickly so that we can have
at least some of this in 5.20.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-07-18 6:40 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support Jianmin Lv
2022-07-16 18:10 ` Marc Zyngier
2022-07-17 1:05 ` Jianmin Lv
2022-07-18 12:28 ` Jianmin Lv
2022-07-18 13:26 ` Marc Zyngier
2022-07-15 7:05 ` [PATCH V15 02/15] APCI: irq: Add support for multiple GSI domains Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 04/15] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 05/15] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 06/15] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 07/15] irqchip: remove COMPILE_TEST for pch-pic and pch-msi Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 08/15] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 09/15] irqchip/loongson-pch-msi: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 10/15] irqchip/loongson-htvec: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 11/15] irqchip/loongson-liointc: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 12/15] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 13/15] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 14/15] irqchip: Add LoongArch CPU " Jianmin Lv
2022-07-15 15:11 ` Huacai Chen
2022-07-17 12:02 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 15/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
2022-07-16 18:39 ` [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Marc Zyngier
2022-07-17 1:06 ` Jianmin Lv
2022-07-17 10:02 ` Marc Zyngier
2022-07-17 11:29 ` Jianmin Lv
2022-07-17 14:08 ` Huacai Chen
2022-07-17 14:43 ` Marc Zyngier
2022-07-18 2:38 ` Huacai Chen
2022-07-18 6:43 ` Marc Zyngier
2022-07-18 8:35 ` Huacai Chen
2022-07-17 14:49 ` Marc Zyngier
2022-07-18 1:07 ` Jianmin Lv
2022-07-18 6:39 ` Marc Zyngier [this message]
2022-07-18 8:29 ` Jianmin Lv
2022-07-18 8:39 ` Huacai Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87fsiy53h3.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=chenhuacai@loongson.cn \
--cc=guohanjun@huawei.com \
--cc=jiaxun.yang@flygoat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=loongarch@lists.linux.dev \
--cc=lorenzo.pieralisi@arm.com \
--cc=lvjianmin@loongson.cn \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox