From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7C63C433F5 for ; Mon, 25 Apr 2022 17:06:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236250AbiDYRJI (ORCPT ); Mon, 25 Apr 2022 13:09:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243722AbiDYRJF (ORCPT ); Mon, 25 Apr 2022 13:09:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7948038DA1; Mon, 25 Apr 2022 10:06:00 -0700 (PDT) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1650906359; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=ZUDdu1OQnuiL9GvFQHLzieqdApEYcfcerAmFX1ae7Fo=; b=kOy/628PH7EV8vd8Bt7kZYGVV4HH2pzB4IOTaqLluAxvnHwNnpQgoIs22zk31UBsLyiO+g pawUq2PFZuAhwQYxXo2cs7jipQTA4E3eFOYp8u3t/RoivhkrCf5YorU/t3tH5W4NX/IpTm TKM/NYt8SjOfKI3TzCEp1ds+AU0Iw8xTIbAI4UfR0iawo9YEe4k+ML9D4Z8QR+Ylv2KQM2 o5tkv5qW+yvlsjcCEu/7ahiIBuqOyLV83Mxe1aXMquFFyuYKauKIey7Gb0RkvSeywP3pZD 6+F5lyl9VUiubCZbFwfoOUZ/ZEpARHDC4VKKOw6F/pPiB10jkkCjW4jC2oyG5A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1650906359; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=ZUDdu1OQnuiL9GvFQHLzieqdApEYcfcerAmFX1ae7Fo=; b=rWgCcD6eod8vPhzNBba08C1rj2XHbFC5P7XdDbrtkk5CwN0PDscGntrk8gXPB4CyWzdoyQ YnRFHLfe4Mhyn7AQ== To: Adrian Hunter , Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , "linux-kernel@vger.kernel.org" , Ingo Molnar , Borislav Petkov , Dave Hansen , "x86@kernel.org" , "kvm@vger.kernel.org" , H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan , "jgross@suse.com" , "sdeep@vmware.com" , "pv-drivers@vmware.com" , "pbonzini@redhat.com" , "seanjc@google.com" , "kys@microsoft.com" , "sthemmin@microsoft.com" , "virtualization@lists.linux-foundation.org" , "Andrew.Cooper3@citrix.com" , "Hall, Christopher S" Subject: Re: [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock In-Reply-To: References: <20220214110914.268126-1-adrian.hunter@intel.com> <20220214110914.268126-4-adrian.hunter@intel.com> <853ce127-25f0-d0fe-1d8f-0b0dd4f3ce71@intel.com> <30383f92-59cb-2875-1e1b-ff1a0eacd235@intel.com> <013b5425-2a60-e4d4-b846-444a576f2b28@intel.com> <6f07a7d4e1ad4440bf6c502c8cb6c2ed@intel.com> <50fd2671-6070-0eba-ea68-9df9b79ccac3@intel.com> <87ilqx33vk.ffs@tglx> Date: Mon, 25 Apr 2022 19:05:58 +0200 Message-ID: <87fsm114ax.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 25 2022 at 16:15, Adrian Hunter wrote: > On 25/04/22 12:32, Thomas Gleixner wrote: >> It's hillarious, that we still cling to this pvclock abomination, while >> we happily expose TSC deadline timer to the guest. TSC virt scaling was >> implemented in hardware for a reason. > > So you are talking about changing VMX TCS Offset on every VM-Entry to try to hide > the time jumps when the VM is scheduled out? Or neglect that and just let the time > jumps happen? > > If changing VMX TCS Offset, how can TSC be kept consistent between each VCPU i.e. > wouldn't that mean each VCPU has to have the same VMX TSC Offset? Obviously so. That's the only thing which makes sense, no? Thanks, tglx