From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-43170.protonmail.ch (mail-43170.protonmail.ch [185.70.43.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94A0B305680 for ; Wed, 15 Jul 2026 13:52:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.170 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784123534; cv=none; b=kR+wA/D5ArCKIQq50KCjxOXvD+LFnbswMFQVYf/wmiID60b8BDIhViG1a6zLF1ORqePVXwxE53XzHGhnIlJF+CKQG+p5ed2OZYJsus8VswswQ/OQjzF4aSQl8+AthH7Q3mDCecHu9gEdJHO7quz3CT4l7B4+LAlxlOHarUCk9Js= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784123534; c=relaxed/simple; bh=UDCxRirisfN6uyLux6/NztFWSmSCbhNLIdUjj9NMzD4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=t1+w7UOAdTzOvRxtDmKy5+yYspDHnBAcV1jAZ4b0VsdZmt7GsfxoUar7CT/geXfqSNcm5rMtGFbwjPflar36Lve5w3HuAx4j0si6EpaY3JiQ0pb7Pq2EQgB9QYBgDvuEQ85x2mQrtHkKZuMveBTGiz7FXJn4kSEHB8hv6mJb0F8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com; spf=pass smtp.mailfrom=geanix.com; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b=a0Bkiclv; arc=none smtp.client-ip=185.70.43.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=geanix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b="a0Bkiclv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=geanix.com; s=protonmail3; t=1784123528; x=1784382728; bh=UDCxRirisfN6uyLux6/NztFWSmSCbhNLIdUjj9NMzD4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=a0Bkiclvw7YtsGdiNjijqEeosPqVmlBJqkPRQOPVjRIcWdpBc5/QHRK6DQJprrq+t IfvVn2dizCjb17bdJFwICujNj8H6+pvdUjbsWcadr3arvnYa46wdSmqXScdp2Ki9Va Todt33JafTXncgGHC7VTBIY2pY+XfoMh7SZi4GmxyzJKjEpI5E+igZp837cHzF7U8Q mJpF3MPRFuxliBSQwWyzwUi9GCbyFfrfu/9Y/+1EQcHFMFBzZ+dC+8kIk5yXU0PYcx 4PouPhkKWaSEpPYvHTCfQNyZ4pIxTrrwiztTovh8S1cscxjYwpmzjtxHP6FUohyo+3 2V1fw1pkrQYUA== X-Pm-Submission-Id: 4h0czp2zL3z2ScqH From: Esben Haabendal To: "AngeloGioacchino Del Regno" Cc: "Gary Bisson" , "Chun-Kuang Hu" , "Philipp Zabel" , "David Airlie" , "Simona Vetter" , "Matthias Brugger" , , , , , "Adam Thiede" , "Thorsten Leemhuis" Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable In-Reply-To: <65558ccc-4f2c-492d-8c74-627d27dce864@collabora.com> (AngeloGioacchino Del Regno's message of "Wed, 15 Jul 2026 15:40:37 +0200") References: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> <8733xko1ms.fsf@geanix.com> <0f719c00-3cf5-4403-afbf-713b07255981@collabora.com> <65558ccc-4f2c-492d-8c74-627d27dce864@collabora.com> Date: Wed, 15 Jul 2026 15:52:05 +0200 Message-ID: <87h5m0mkca.fsf@geanix.com> User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain "AngeloGioacchino Del Regno" writes: > On 7/15/26 15:36, Gary Bisson wrote: >> Hi, >> >> On Wed, Jul 15, 2026 at 03:25:11PM +0200, AngeloGioacchino Del Regno wrote: >>> On 7/15/26 14:53, Esben Haabendal wrote: >>>> Gary Bisson writes: >>>> >>>>> Some bridges, such as the TI SN65DSI83, require the HS clock to be >>>>> running in order to lock its PLL during its own pre-enable function. >>>>> >>>>> Without this change, the bridge gives the following error: >>>>> sn65dsi83 14-002c: failed to lock PLL, ret=-110 >>>>> sn65dsi83 14-002c: Unexpected link status 0x01 >>>>> sn65dsi83 14-002c: reset the pipe >>>>> >>>>> Move the necessary functions from enable to pre-enable. >>>>> >>>>> Signed-off-by: Gary Bisson >>>> >>>> Hi >>>> >>>> I have run into the same problem, but in combination with another >>>> pipeline. I am seeing same problem with an i.MX8 using the nwl-dsi >>>> bridge and the dcss driver. >>>> >>>> I have submitted a fix that adresses the problem in the ti-sn65dsi83 >>>> driver instead. With a bit of luck, it can replace the fix proposed in >>>> this thread. >>>> >>>> See https://lore.kernel.org/all/20260711-ti-sn65dsi83-fixes-v1-2-d85eb5342b98@geanix.com/ >> >> Thanks, just tried it on 7.2-rc3 with my patch reverted and confirm that >> it works too. My assumption was that the SN65DSI83 was locking the PLL >> earlier for some specific reason and therefore was reluctant to change >> it. >> >>>> /Esben >>> >>> That clarifies a lot of things. >>> >>> The patch on mtk_dsi shall be reverted then. >> >> Angelo, do you want me to offer the revert patch? Should I wait to see >> how the other thread goes? >> > > Gary, yes please, send a revert and make sure to explain the reason why > we're reverting this in the commit description :-) Maybe test if my fix actually solves the problem with the mtk_dsi driver also ;) /Esben