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bh=xTX81h9G8aXD+7JUezIJElO7ofVmpUIJ9dOvTE7EZYU=; b=kEtrPH98gylBd4+JZ89TFaO4BcZthV9Wte4mp9eciEjpkdsnOFEF8MSv4ePIb8dfiQGS7H qKQVtn1ytcQT64zRU7moFryKdbHsJTIJfmg1WoYBwB66fOWVquEW+y4Xe213lo/2gH+Kxr NyBl7ZEpb2xzftcO9W7Me8ix1yX9tic+NUdZL0XWl16tQC4Cso9JSg1X+tdfMUDQN135LK qOr/YuP5KTErCd+EeS7lx5tS6xF7eL6ogeVKumVPyXpUc6BB+FYEiX1BYCIT/pLkPpkvil xZqE/cU4JyQnGJFuMsj07dRw9EfpQSTe7b9XABKFNrN1WcPt6FQJ1cdK5Ge7tg== From: Miquel Raynal To: Md Sadre Alam Cc: Gabor Juhos , Mark Brown , Manivannan Sadhasivam , Richard Weinberger , Vignesh Raghavendra , "Varadarajan Narayanan" , Sricharan Ramabadhran , , , , Subject: Re: [PATCH next 2/2] spi: spi-qpic-snand: add support for 8 bits ECC strength In-Reply-To: (Md Sadre Alam's message of "Wed, 21 May 2025 11:08:02 +0530") References: <20250502-qpic-snand-8bit-ecc-v1-0-95f3cd08bbc5@gmail.com> <20250502-qpic-snand-8bit-ecc-v1-2-95f3cd08bbc5@gmail.com> <8aa3d4da-da3e-2af4-e0f9-cd56d6259d8f@quicinc.com> <878qn2nsa0.fsf@bootlin.com> <16195524-1f31-4968-a3fd-f3d24f1c4223@gmail.com> <87msbhezjf.fsf@bootlin.com> <007881c9-e03c-1473-d8eb-53fbad8c6a8e@quicinc.com> <87frh4ej87.fsf@bootlin.com> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Wed, 21 May 2025 09:52:31 +0200 Message-ID: <87h61e8kow.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtddtgddvhedvucdltddurdegfedvrddttddmucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuifetpfffkfdpucggtfgfnhhsuhgsshgtrhhisggvnecuuegrihhlohhuthemuceftddunecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvfevufgjfhgffffkgggtgfesthhqredttderjeenucfhrhhomhepofhiqhhuvghlucftrgihnhgrlhcuoehmihhquhgvlhdrrhgrhihnrghlsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeffgefhjedtfeeigeduudekudejkedtiefhleelueeiueevheekvdeludehiedvfeenucfkphepledtrdekledrudeifedruddvjeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeeltddrkeelrdduieefrdduvdejpdhhvghloheplhhotggrlhhhohhsthdpmhgrihhlfhhrohhmpehmihhquhgvlhdrrhgrhihnrghlsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopeduvddprhgtphhtthhopehquhhitggpmhgurghlrghmsehquhhitghinhgtrdgtohhmpdhrtghpthhtohepjhegghekhiejsehgmhgrihhlrdgtohhmpdhrtghpthhtohepsghrohhonhhivgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepmhgrnhhivhgrnhhnrghnrdhsrgguhhgrshhivhgrmheslhhinhgrrhhordhorhhgpdhrtghpthhtoheprhhitghhrghrugesnhhou gdrrghtpdhrtghpthhtohepvhhighhnvghshhhrsehtihdrtghomhdprhgtphhtthhopehquhhitggpvhgrrhgruggrsehquhhitghinhgtrdgtohhmpdhrtghpthhtohepqhhuihgtpghsrhhitghhrghrrgesqhhuihgtihhntgdrtghomh X-GND-Sasl: miquel.raynal@bootlin.com On 21/05/2025 at 11:08:02 +0530, Md Sadre Alam wr= ote: > Hi, > > On 5/16/2025 7:44 PM, Miquel Raynal wrote: >>=20 >>>>> Interestingly enough, it reports the correct number of bit errors now. >>>>> For me it seems, that the hardware reports the number of the corrected >>>>> *bytes* instead of the corrected *bits*. >>>> I doubt that, nobody counts bytes of errors. >>>> You results are surprising. I initially though in favour of a software >>>> bug, but then it looks even weirder than that. Alam? >>> I have checked with HW team , the QPIC ECC HW engine reports the bit >>> error byte wise not bit wise. >>> >>> e.g >>> Byte0 --> 2-bitflips --> QPIC ECC counts 1 only >>> Byte1 --> 3-bitflips --> QPIC ECC counts 1 only >>> Byte2 --> 1-bitflips --> QPIC ECC counts 1 only >>> Byte3 --> 4-bitflips --> QPIC ECC counts 1 only (in 8-bit ecc) >>> Byte4 --> 6-bitflips --> QPIC ECC counts 1 only (in 8-bit ecc) >>> >>> Hope this can clearify the things now. >> o_O ???? >> How is that even useful? This basically means UBI will never refresh >> the >> data because we will constantly underestimate the number of bitflips! We >> need to know the actual number, this averaging does not make any sense >> for Linux. Is there another way to get the raw number of bitflips? > I have re-checked with HW team, unfortunately currently there is no > register fields available to get the raw number of bit flips. But > for newer chipset they have fixed this issue. But currently the QPIC > QPIC_NANDC_BUFFER_STATUS | 0x79B0018 register bit-8 will get set if > there is uncorrectable bitflips happened. > > For 4-bit ECC if 5-bit raw bit flips happened then bit-8 will get set in > QPIC_NANDC_BUFFER_STATUS. > > similar for 8-bit ECC if 9-bit raw bit flips happened then bit-8 will > get set in QPIC_NANDC_BUFFER_STATUS. I believe the unrecoverable situation is handled correctly. What is not is the fact that we care about the number of bitflips before having a failure because if it reaches a certain threshold (typically 2/3 of the strength) the upper layer is responsible of moving the data around to avoid loosing it. You need to identify the hardware revision that fixed it and provide a warning otherwise, or at least a comment in the code... Thanks, Miqu=C3=A8l