Re: [PATCH] irqchip/qcom-pdc: Workaround hardware register bug on X1E80100

Johan Hovold
2025-02-13T17:14:42Z

On Thu, Feb 13, 2025 at 06:04:00PM +0100, Stephan Gerhold wrote:
> On X1E80100, there is a hardware bug in the register logic of the
> IRQ_ENABLE_BANK register. While read accesses work on the normal address,
> all write accesses must be made to a shifted address. Without a workaround
> for this, the wrong interrupt gets enabled in the PDC and it is impossible
> to wakeup from deep suspend (CX collapse).
>
> This has not caused problems so far, because the deep suspend state was not
> enabled. We need a workaround now since work is ongoing to fix this.
>
> Introduce a workaround for the problem by matching the qcom,x1e80100-pdc
> compatible and shift the write address by the necessary offset.
>
> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>

I've been running with this patch for a while now and it allows me to
wake up from deep suspend on the X1E CRD using the power button (or
GPIO interrupts with further patches):

Tested-by: Johan Hovold <johan+linaro@kernel.org>

Johan