[PATCH 0/2] riscv: Add "Code:", and decodecode support

[PATCH 0/2] riscv: Add "Code:", and decodecode support

[Björn Töpel]

From: Björn Töpel <bjorn@rivosinc.com>

RISC-V does not have "Code:" dumps in the Oops output. This series
adds that, together with scripts/decodecode support.

Thanks,
Björn

Björn Töpel (2):
  riscv: Add "Code:" to RISC-V splats
  scripts/decodecode: Add support for RISC-V

 arch/riscv/kernel/traps.c | 31 ++++++++++++++++++++++++++++++-
 scripts/decodecode        | 12 +++++++++++-
 2 files changed, 41 insertions(+), 2 deletions(-)


base-commit: 689968db7b6145b2e4beb8b472d31162ffa5ad7d
-- 
2.37.2

[PATCH 1/2] riscv: Add "Code:" to RISC-V splats

[Björn Töpel]

From: Björn Töpel <bjorn@rivosinc.com>

Add "Code:" output to RISC-V splats. Mimic x86-64's byte-for-byte
dumps.

An example:
  Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000
  Oops [#1]
  Modules linked in:
  CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.2.0-rc3-00063-g0ce8b1377b2b-dirty #3
  Hardware name: riscv-virtio,qemu (DT)
  epc : kernel_init+0xc8/0x10e
   ra : kernel_init+0x70/0x10e
  epc : ffffffff80bd9938 ra : ffffffff80bd98e0 sp : ff2000000060bec0
   gp : ffffffff81730b28 tp : ff6000007ff00000 t0 : 7974697275636573
   t1 : 0000000000000000 t2 : 3030303270393d6e s0 : ff2000000060bee0
   s1 : ffffffff81732028 a0 : 0000000000000000 a1 : ff6000008157e600
   a2 : 0000000000000002 a3 : ffffffff8176a470 a4 : 0000000000000000
   a5 : 000000000000000a a6 : 0000000000000118 a7 : ff6000008157e600
   s2 : 0000000000000000 s3 : 0000000000000000 s4 : 0000000000000000
   s5 : 0000000000000000 s6 : 0000000000000000 s7 : 0000000000000000
   s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
   s11: 0000000000000000 t3 : ffffffff81185ff0 t4 : 0000000000000022
   t5 : 000000000000003d t6 : 0000000000000000
  status: 0000000200000120 badaddr: 0000000000000000 cause: 000000000000000f
  [<ffffffff80003528>] ret_from_exception+0x0/0x16
  Code: 2a 86 79 d1 8c 60 17 a5 69 00 13 05 65 38 ef d0 2e db a9 47 <1c> c1 17 a5
  ---[ end trace 0000000000000000 ]---
  Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
  SMP: stopping secondary CPUs
  ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---

Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
---
 arch/riscv/kernel/traps.c | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 549bde5c970a..efadff4190e0 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -29,6 +29,33 @@ int show_unhandled_signals = 1;
 
 static DEFINE_SPINLOCK(die_lock);
 
+static void dump_kernel_instr(const char *loglvl, struct pt_regs *regs)
+{
+#define PROLOGUE_SIZE 20
+#define EPILOGUE_SIZE 3
+#define OPCODE_BUFSIZE (PROLOGUE_SIZE + 1 + EPILOGUE_SIZE)
+	u8 opcodes[OPCODE_BUFSIZE];
+	unsigned long prologue = regs->epc - PROLOGUE_SIZE;
+
+	if (user_mode(regs))
+		return;
+
+	switch (copy_from_kernel_nofault(opcodes, (u8 *)prologue, sizeof(opcodes))) {
+	case 0:
+		printk("%sCode: %" __stringify(PROLOGUE_SIZE) "ph <%02x> %"
+		       __stringify(EPILOGUE_SIZE) "ph\n", loglvl, opcodes,
+		       opcodes[PROLOGUE_SIZE], opcodes + PROLOGUE_SIZE + 1);
+		break;
+	case -EPERM:
+		/* No access to the user space stack of other tasks. Ignore. */
+		break;
+	default:
+		printk("%sCode: Unable to access opcode bytes at 0x%lx.\n",
+		       loglvl, prologue);
+		break;
+	}
+}
+
 void die(struct pt_regs *regs, const char *str)
 {
 	static int die_counter;
@@ -43,8 +70,10 @@ void die(struct pt_regs *regs, const char *str)
 
 	pr_emerg("%s [#%d]\n", str, ++die_counter);
 	print_modules();
-	if (regs)
+	if (regs) {
 		show_regs(regs);
+		dump_kernel_instr(KERN_EMERG, regs);
+	}
 
 	cause = regs ? regs->cause : -1;
 	ret = notify_die(DIE_OOPS, str, regs, 0, cause, SIGSEGV);
-- 
2.37.2

[PATCH 2/2] scripts/decodecode: Add support for RISC-V

[Björn Töpel]

From: Björn Töpel <bjorn@rivosinc.com>

RISC-V has some GNU disassembly quirks, e.g. it requires '-D' to
properly disassemble .byte directives similar to Arm [1]. Further, GNU
objdump groups RISC-V instruction by 2 or 4 byte chunks, instead doing
byte-for-byte.

Add the required switches, and translate from short/word to bytes when
ARCH is "riscv".

An example how to invoke decodecode for RISC-V:
  $ echo 'Code: 64 c9 29 a0 17 d4 1f 01 13 04 44
  b8 93 92 38 00 16 94 00 60 <02> 94 aa e8' |  \
  AFLAGS="-march=rv64imac_zicbom_zihintpause"  \
  ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- ./scripts/decodecode
  Code: 64 c9 29 a0 17 d4 1f 01 13 04 44 b8 93 92 38 00 16 94 00 60 <02> 94 aa e8
  All code
  ========
     0:   c964                    c.sw    s1,84(a0)
     2:   a029                    c.j     c <.text+0xc>
     4:   011fd417                auipc   s0,0x11fd
     8:   b8440413                addi    s0,s0,-1148 # 11fcb88 <.text+0x11fcb88>
     c:   00389293                slli    t0,a7,0x3
    10:   9416                    c.add   s0,t0
    12:   6000                    c.ld    s0,0(s0)
    14:*  9402                    c.jalr  s0              <-- trapping instruction
    16:   e8aa                    c.sdsp  a0,80(sp)

  Code starting with the faulting instruction
  ===========================================
     0:   9402                    c.jalr  s0
     2:   e8aa                    c.sdsp  a0,80(sp)

[1] https://sourceware.org/bugzilla/show_bug.cgi?id=10263

Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
---
 scripts/decodecode | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/scripts/decodecode b/scripts/decodecode
index b28fd2686561..8fe71c292381 100755
--- a/scripts/decodecode
+++ b/scripts/decodecode
@@ -93,6 +93,11 @@ disas() {
 		${CROSS_COMPILE}strip $t.o
 	fi
 
+	if [ "$ARCH" = "riscv" ]; then
+		OBJDUMPFLAGS="-M no-aliases --section=.text -D"
+		${CROSS_COMPILE}strip $t.o
+	fi
+
 	if [ $pc_sub -ne 0 ]; then
 		if [ $PC ]; then
 			adj_vma=$(( $PC - $pc_sub ))
@@ -126,8 +131,13 @@ get_substr_opcode_bytes_num()
 	do
 		substr+="$opc"
 
+		opcode="$substr"
+		if [ "$ARCH" = "riscv" ]; then
+			opcode=$(echo $opcode | tr ' ' '\n' | tac | tr -d '\n')
+		fi
+
 		# return if opcode bytes do not match @opline anymore
-		if ! echo $opline | grep -q "$substr";
+		if ! echo $opline | grep -q "$opcode";
 		then
 			break
 		fi
-- 
2.37.2

Re: [PATCH 1/2] riscv: Add "Code:" to RISC-V splats

[Andreas Schwab]

On Jan 13 2023, Björn Töpel wrote:

> From: Björn Töpel <bjorn@rivosinc.com>
>
> Add "Code:" output to RISC-V splats. Mimic x86-64's byte-for-byte
> dumps.

RISC-V insns are organised in 16-bit parcels, it probably make sense to
present them that way.

-- 
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."

Re: [PATCH 1/2] riscv: Add "Code:" to RISC-V splats

[Björn Töpel]

Andreas Schwab <schwab@linux-m68k.org> writes:

>> Add "Code:" output to RISC-V splats. Mimic x86-64's byte-for-byte
>> dumps.
>
> RISC-V insns are organised in 16-bit parcels, it probably make sense to
> present them that way.

Good point! I'll spin a v2.


Thanks for having a look,
Björn