From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 074ADC433E0 for ; Fri, 12 Feb 2021 11:29:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CBE6464E65 for ; Fri, 12 Feb 2021 11:29:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229929AbhBLL30 (ORCPT ); Fri, 12 Feb 2021 06:29:26 -0500 Received: from mga05.intel.com ([192.55.52.43]:24929 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229608AbhBLL3W (ORCPT ); Fri, 12 Feb 2021 06:29:22 -0500 IronPort-SDR: 4bb3RBDLKo2zOYT7DFfOFOI1adCHZC6rVwScRjKFGHVykPp5JcsUulY/7731HGxS6FGbS26aZa ZTQwuPxcI/2Q== X-IronPort-AV: E=McAfee;i="6000,8403,9892"; a="267241350" X-IronPort-AV: E=Sophos;i="5.81,173,1610438400"; d="scan'208";a="267241350" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2021 03:28:42 -0800 IronPort-SDR: 10O1SAjzXR69ChWDX/cN8MLqIhMl+B9DJrP/wpC0lbj/31h38bep16Q2KxFSH6WHcCsqjDYRfk 71qik/sLdFaA== X-IronPort-AV: E=Sophos;i="5.81,173,1610438400"; d="scan'208";a="397943677" Received: from mpetrica-mobl.ger.corp.intel.com (HELO localhost) ([10.252.54.176]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2021 03:28:38 -0800 From: Jani Nikula To: Lyude Paul , dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Sean Paul , open list Subject: Re: [RFC v4 05/11] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit In-Reply-To: <20210208233902.1289693-6-lyude@redhat.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20210208233902.1289693-1-lyude@redhat.com> <20210208233902.1289693-6-lyude@redhat.com> Date: Fri, 12 Feb 2021 13:28:35 +0200 Message-ID: <87h7mhcyos.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 08 Feb 2021, Lyude Paul wrote: > Get rid of the extraneous switch case in here, and just open code > edp_backlight_mode as we only ever use it once. > > v4: > * Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not > DP_EDP_BACKLIGHT_CONTROL_MODE_MASK - imirkin > > Signed-off-by: Lyude Paul > --- > .../gpu/drm/i915/display/intel_dp_aux_backlight.c | 15 ++------------- > 1 file changed, 2 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > index c37ccc8538cb..57218faed4a3 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > @@ -382,7 +382,7 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state, > struct intel_dp *intel_dp = intel_attached_dp(connector); > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > struct intel_panel *panel = &connector->panel; > - u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode; > + u8 dpcd_buf, new_dpcd_buf; > u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count; > > if (drm_dp_dpcd_readb(&intel_dp->aux, > @@ -393,12 +393,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state, > } > > new_dpcd_buf = dpcd_buf; > - edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK; > > - switch (edp_backlight_mode) { > - case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM: > - case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET: > - case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT: > + if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { > new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK; > new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; > > @@ -406,13 +402,6 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state, > pwmgen_bit_count) != 1) What baseline is this on? None that I can think of have the above != 1, they're all < 0 AFAICT. BR, Jani. > drm_dbg_kms(&i915->drm, > "Failed to write aux pwmgen bit count\n"); > - > - break; > - > - /* Do nothing when it is already DPCD mode */ > - case DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD: > - default: > - break; > } > > if (panel->backlight.edp.vesa.pwm_freq_pre_divider) { -- Jani Nikula, Intel Open Source Graphics Center