From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6616117D354; Wed, 4 Dec 2024 09:04:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733303072; cv=none; b=f+z+qVKUNL1XBkd2nlM4RffSwpcZ/otCZkUE1Aoa9Qczze2gcEoKYKAM109Dd0ESQssvv/B7o4ZGUZn9sxWQoYMWYOUV9DbKb8R4H4YRtKrh3emOkC1hXTZTlGPYXmyI7Y/YrWJ1tvAL/NSa3XWkyL93A4iiqFNN72PmBoIOBAg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733303072; c=relaxed/simple; bh=VT8ZfVdCX2f7yWT+xNjlJWjbNeNrv22Jv1EIIDNEunU=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=eGxWWYncJRgeoluubJ+Xs/8Yi0r9ScKBNnrpjsZm3h89q2rgS5/H+0CO8ZfDVr6sGBMULz29miXEIGYAKbk1dhwU2chJTfasVt+RqW7V5YlzxCxWq5IBA3V8nC2ymR0GgmRpHbeIYnt873PUjgUwB1oOk7+eqGo0mhsxsAkqakY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oUPDjmdd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oUPDjmdd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C7AE8C4CED1; Wed, 4 Dec 2024 09:04:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733303071; bh=VT8ZfVdCX2f7yWT+xNjlJWjbNeNrv22Jv1EIIDNEunU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=oUPDjmddCGZGbyLZZD1MzXPndzo55vLhSrq1uC/YHc1lbEAgA1APGQ8GTVh+Ba+4I tM78cUufghWaVjkEuv5mlwycA4BnNi6/0jwXnBJin8Xn10MAyTpk9IJBm3KQgFJZK3 /LuOEDPh+YBA7j8D4GGEEO49E/7IFtGsUwGfx9LVrPWyu6daToQTaCYwlgqDK2CNhv YZg7YioF2Pl6uVVusLaFz7FMptlyRuSgtzJAs/L9Rk3BpMmNv1Ypk859PQebCvP1/5 hrd2LC3EHi/nTt5TV8c0LB6mKrNGJymhVPC6FqYPbIlwvDbdITYMgEVtIj5OLYXC8J D8EPQ9a++hAXw== Received: from 82-132-237-135.dab.02.net ([82.132.237.135] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tIlJ6-000Nlg-VV; Wed, 04 Dec 2024 09:04:29 +0000 Date: Wed, 04 Dec 2024 09:04:26 +0000 Message-ID: <87ikrzstt1.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 05/14] KVM: arm64: Always allow fixed cycle counter In-Reply-To: References: <20241203193220.1070811-1-oliver.upton@linux.dev> <20241203193220.1070811-6-oliver.upton@linux.dev> <87ldwwsbad.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 82.132.237.135 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mizhang@google.com, coltonlewis@google.com, rananta@google.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 03 Dec 2024 22:32:38 +0000, Oliver Upton wrote: > > On Tue, Dec 03, 2024 at 09:32:10PM +0000, Marc Zyngier wrote: > > On Tue, 03 Dec 2024 19:32:11 +0000, > > Oliver Upton wrote: > > > > > > The fixed CPU cycle counter is mandatory for PMUv3, so it doesn't make a > > > lot of sense allowing userspace to filter it. Only apply the PMU event > > > filter to *programmed* event counters. > > > > But that's a change in ABI, isn't it? We explicitly say in the > > documentation that the cycle counter can be filtered by specifying > > event 0x11. > > Yeah... A bit of a dirty shortcut I took because I don't like the ABI, > but distaste isn't enough to break it :) > > > More importantly, the current filtering works in terms of events, and > > not in terms of counters. > > > > Instead of changing the ABI, how about simply not supporting filtering > > on such non-compliant HW? Surely that would simplify a few things. > > Yeah, that sounds reasonable. Especially if we allow programmable event > counters where the event ID space doesn't match the architecture. Another thing I have been wondering is if a slightly better approach would be to move some of the handling to the PMU driver itself, and let it emulate PMUv3 if it can. This would allow conversion of event numbers in situ rather than polluting the PMUv3 code in KVM. M. -- Without deviation from the norm, progress is not possible.