From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F8B0C433EF for ; Sun, 17 Jul 2022 10:03:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232796AbiGQKDE (ORCPT ); Sun, 17 Jul 2022 06:03:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229476AbiGQKDD (ORCPT ); Sun, 17 Jul 2022 06:03:03 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 216C6AE47 for ; Sun, 17 Jul 2022 03:03:02 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C550FB8074A for ; Sun, 17 Jul 2022 10:03:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7464EC3411E; Sun, 17 Jul 2022 10:02:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658052179; bh=wEAd2qSvbkYxJle9WMnfQqNa/vbPEDsBIBxaIP4bzJg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=YtVHPZe6fiYIOV3ifgsOGmiyk3SYU8+OF8uiPpb2OADo/z/Pii+0IukakxVQegq5Q zdTBZ6eVyHzBnMb2xNGntEGo8Tb+EkaPEAQx9cYnmz+TPZwJRVNCXGg7q1TEJE36/V vyEKnQTYWF3Ajeh80ZHhEP41LN4ywvl8TMOxODcZKWP8ulybzU3bUKluxiMx91VGzE PLs/320HhDyMr9U7f67cRPVAhWfapGn5p5lf7U3UhV9ZFHbPueZqibakf1aAy4Hx9C h66igdeDRB1U4/auyU19PXCx9Ebh1uL7y5No7v4czq3dOyaRxh8ZytnZzI+0Yo0Koi HNwmvmRguiCkg== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oD173-007zbM-2Z; Sun, 17 Jul 2022 11:02:57 +0100 Date: Sun, 17 Jul 2022 11:02:51 +0100 Message-ID: <87ilnw3vlg.wl-maz@kernel.org> From: Marc Zyngier To: Jianmin Lv Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Hanjun Guo , Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen Subject: Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers In-Reply-To: <6e9def1e-31fe-787d-1b2b-a328424352f0@loongson.cn> References: <1657868751-30444-1-git-send-email-lvjianmin@loongson.cn> <87less52bx.wl-maz@kernel.org> <6e9def1e-31fe-787d-1b2b-a328424352f0@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lvjianmin@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, guohanjun@huawei.com, lorenzo.pieralisi@arm.com, jiaxun.yang@flygoat.com, chenhuacai@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 17 Jul 2022 02:06:12 +0100, Jianmin Lv wrote: >=20 >=20 >=20 > On 2022/7/17 =E4=B8=8A=E5=8D=882:39, Marc Zyngier wrote: > > On Fri, 15 Jul 2022 08:05:36 +0100, > > Jianmin Lv wrote: > >>=20 > >> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. > >> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit > >> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its > >> boot protocol LoongArch-specific interrupt controllers (similar to API= C) > >> are already added in the ACPI Specification 6.5(which may be published= in > >> early June this year and the board is reviewing the draft). > >>=20 > >> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only > >> work together with LS7A chipsets. The irq chips in LoongArch computers > >> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O > >> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), > >> HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main > >> Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controll= er > >> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). > >=20 > > [...] > >=20 > > Compiling this series for loongarch with loongson3_defconfig on top of > > 5.19-rc3 results in the following: > >=20 > > loongarch64-linux-ld: drivers/irqchip/irq-loongson-eiointc.o: in functi= on `.L60': > > irq-loongson-eiointc.c:(.init.text+0x4c): undefined reference to `pch_m= si_acpi_init' > > loongarch64-linux-ld: drivers/irqchip/irq-loongson-htvec.o: in function= `pch_msi_parse_madt': > > irq-loongson-htvec.c:(.init.text+0x14): undefined reference to `pch_msi= _acpi_init' > > make: *** [Makefile:1164: vmlinux] Error 1 > >=20 > > I *really* would have expected this series to be in a better shape > > after over 15 rounds, but it looks like I'm expecting too much. I > > haven't investigated the breakage, but this should (at the very least) > > pass the defconfig test and optional drivers not being selected. > >=20 > > The corresponding MIPS configuration seems to build fine. > >=20 > > M. > >=20 >=20 > Hi, Marc >=20 > Sorry for that first, pch_msi_acpi_init is defined in pch_msi driver > which is compiled depend on CONFIG_PCI, and I test the patches each > time with PCI patches and other(or else, kernel can not be boot), so > I'm ok for testing the patches. The PCI patches has been accepted by > PCI maintainers and will be merged in this merge window. But each series *must* at the very least compile in isolation. >=20 > I don't know how to deal with this situation. Should I add *#ifdef > CONFIG_PCI* at position of calling pch_msi_acpi_init or some other > way? You could try something like this, which results in a kernel that fully links with defconfig and no additional patch: diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/= irq.h index ca468564fc85..4479d95867ec 100644 --- a/arch/loongarch/include/asm/irq.h +++ b/arch/loongarch/include/asm/irq.h @@ -99,8 +99,17 @@ int htvec_acpi_init(struct irq_domain *parent, struct acpi_madt_ht_pic *acpi_htvec); int pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc); +#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI) int pch_msi_acpi_init(struct irq_domain *parent, - struct acpi_madt_msi_pic *acpi_pchmsi); + struct acpi_madt_msi_pic *acpi_pchmsi); +#else +static inline int pch_msi_acpi_init(struct irq_domain *parent, + struct acpi_madt_msi_pic *acpi_pchmsi) +{ + return 0; + +} +#endif int pch_pic_acpi_init(struct irq_domain *parent, struct acpi_madt_bio_pic *acpi_pchpic); int find_pch_pic(u32 gsi); But the other issue is that you seem to call this function from two different locations. This cannot be right, as there should be only one probe order, and not multiple. M. --=20 Without deviation from the norm, progress is not possible.