From: Thomas Gleixner <tglx@linutronix.de>
To: Borislav Petkov <bp@alien8.de>
Cc: Ingo Molnar <mingo@kernel.org>,
"Ahmed S. Darwish" <darwi@linutronix.de>,
Ard Biesheuvel <ardb+git@google.com>,
linux-kernel@vger.kernel.org, x86@kernel.org,
Ard Biesheuvel <ardb@kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Brian Gerst <brgerst@gmail.com>,
"Kirill A. Shutemov" <kirill@shutemov.name>
Subject: Re: [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging
Date: Wed, 21 May 2025 22:07:37 +0200 [thread overview]
Message-ID: <87jz69raly.ffs@tglx> (raw)
In-Reply-To: <20250521194819.GGaC4uA6mwlMBoqDMt@fat_crate.local>
On Wed, May 21 2025 at 21:48, Borislav Petkov wrote:
> On Wed, May 21, 2025 at 09:41:00PM +0200, Thomas Gleixner wrote:
>> In the long run we really want to disable user space CPUID and emulate
>> it when the hardware supports CPUID faulting, which should be made an
>> architectural feature IMO.
>
> Both vendors do support it. I probably should do the AMD side. It is about
> time...
Both vendors support it, but it's not an architectural feature and it
really should be one.
That ensures it can't go away just because some hardware dude thinks
again that the three extra gates are overkill as all of this can be
handled in software ....
Thanks,
tglx
next prev parent reply other threads:[~2025-05-21 20:07 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-17 9:16 [PATCH v4 0/6] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-17 9:16 ` [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging Ard Biesheuvel
2025-05-17 14:28 ` Ard Biesheuvel
2025-05-19 8:35 ` Ingo Molnar
2025-05-19 9:40 ` Borislav Petkov
2025-05-19 9:46 ` Ard Biesheuvel
2025-05-19 12:15 ` Borislav Petkov
2025-05-19 12:24 ` Borislav Petkov
2025-05-19 12:25 ` Ard Biesheuvel
2025-05-19 13:08 ` Ingo Molnar
2025-05-19 13:19 ` Borislav Petkov
2025-05-21 15:23 ` Thomas Gleixner
2025-05-21 18:11 ` Borislav Petkov
2025-05-21 18:56 ` Thomas Gleixner
2025-05-21 19:29 ` Borislav Petkov
2025-05-21 19:41 ` Thomas Gleixner
2025-05-21 19:48 ` Borislav Petkov
2025-05-21 20:07 ` Thomas Gleixner [this message]
2025-05-22 7:55 ` Peter Zijlstra
2025-05-22 15:08 ` Sean Christopherson
2025-05-22 19:58 ` Thomas Gleixner
2025-05-22 22:15 ` Sean Christopherson
2025-05-19 12:55 ` [tip: x86/core] x86/cpu: Use a new feature flag for 5-level paging tip-bot2 for Ard Biesheuvel
2025-05-19 13:12 ` Ingo Molnar
2025-05-17 9:16 ` [PATCH v4 2/6] x86/cpu: Move CPU capability override arrays from BSS to __ro_after_init Ard Biesheuvel
2025-05-19 12:01 ` Brian Gerst
2025-05-17 9:16 ` [PATCH v4 3/6] x86/cpu: Allow caps to be set arbitrarily early Ard Biesheuvel
2025-05-17 9:16 ` [PATCH v4 4/6] x86/boot: Set 5-level paging CPU cap before entering C code Ard Biesheuvel
2025-05-17 9:16 ` [PATCH v4 5/6] x86/boot: Drop the early variant of pgtable_l5_enabled() Ard Biesheuvel
2025-05-17 9:16 ` [PATCH v4 6/6] x86/boot: Drop 5-level paging related variables and early updates Ard Biesheuvel
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