From: Marc Zyngier <maz@kernel.org>
To: Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Paul Burton <paulburton@kernel.org>,
Serge Semin <fancer.lancer@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
Chao-ying Fu <cfu@wavecomp.com>
Subject: Re: [PATCH 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu()
Date: Fri, 20 May 2022 09:38:55 +0100 [thread overview]
Message-ID: <87k0agmwdc.wl-maz@kernel.org> (raw)
In-Reply-To: <20220519185125.11686-4-Dragan.Mladjenovic@syrmia.com>
On Thu, 19 May 2022 19:51:16 +0100,
Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com> wrote:
>
> From: Paul Burton <paulburton@kernel.org>
>
> A few pieces of code in the MIPS GIC driver operate on the GIC local
> register block for each online CPU, accessing each via the GIC's
> other/redirect register block. This patch abstracts the process of
> iterating over online CPUs & configuring the other/redirect region to
> access their registers through a new gic_with_each_online_cpu() macro.
>
> This simplifies users of the new macro slightly, and more importantly
> prepares us for handling multi-cluster systems where the register
> configuration will be done via the CM's GCR_CL_REDIRECT register. By
> abstracting all other/redirect block configuration through this macro,
> and the __gic_with_next_online_cpu() function which backs it, users will
> trivially gain support for multi-cluster when it is implemented in
> __gic_with_next_online_cpu().
>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
>
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index ff89b36267dd..4872bebe24cf 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
No SoB from the sender, odd patch format (no ---), and I didn't get a
complete series, which makes it impossible to review things in context
(I don't even know what the series is about).
Please fix things and resend.
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-05-20 8:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-19 18:51 [PATCH 00/12] MIPS: Support I6500 multi-cluster configuration Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 01/12] MIPS: CPS: Add a couple of multi-cluster utility functions Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 02/12] MIPS: GIC: Generate redirect block accessors Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu() Dragan Mladjenovic
2022-05-20 8:38 ` Marc Zyngier [this message]
2022-05-23 10:30 ` Serge Semin
2022-05-19 18:51 ` [PATCH 04/12] irqchip: mips-gic: Support multi-cluster in gic_with_each_online_cpu() Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 05/12] irqchip: mips-gic: Setup defaults in each cluster Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 06/12] irqchip: mips-gic: Multi-cluster support Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 07/12] clocksource: mips-gic-timer: Always use cluster 0 counter as clocksource Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 08/12] clocksource: mips-gic-timer: Enable counter when CPUs start Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 09/12] MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 10/12] MIPS: CPS: Introduce struct cluster_boot_config Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 11/12] MIPS: Report cluster in /proc/cpuinfo Dragan Mladjenovic
2022-05-19 18:51 ` [PATCH 12/12] MIPS: CPS: Boot CPUs in secondary clusters Dragan Mladjenovic
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