From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3B0EC433EF for ; Mon, 21 Mar 2022 09:31:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345908AbiCUJdJ (ORCPT ); Mon, 21 Mar 2022 05:33:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238396AbiCUJdH (ORCPT ); Mon, 21 Mar 2022 05:33:07 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EABB554BF for ; Mon, 21 Mar 2022 02:31:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C57F861248 for ; Mon, 21 Mar 2022 09:31:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D6BFC340E8; Mon, 21 Mar 2022 09:31:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1647855102; bh=sBjg7qgQ6pczYWMz8UKw42GOeHOpY7uX94N0BI51gHo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ByIZ6N/6MPrert/CyCQRL27uNf95TpwDv9nIprg1u89aImqqlPlEt2ipFfwdHHaDq 4K3J4fLYrhvyV30eMOgXJToobLd7achbkdrSb99OnyfgXfpX18hlkwfEGlHljnp4vT CIPAfJCW2Dg3nHT0Jrlv3EeF9oyM+nvAe68zRPfssyQDLHoR50wmgtX5ccPn1cs0mQ xKDOdIkTjVdg5+adYg+if+OHMQr55Th8oqx/sFKhK5fFmaE9OPWnVomyYrQ2vPhHQs BixMU9U4LywmecDE6yPP/DezVP5zGo2dlJ+4QwsccsU2W5q4HSmyEgprUt11yPixAY 06PKRMxXMXgkg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nWEO3-00FuQu-RN; Mon, 21 Mar 2022 09:31:39 +0000 Date: Mon, 21 Mar 2022 09:31:39 +0000 Message-ID: <87k0cny7lw.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: linux-kernel@vger.kernel.org, Andre Przywara , Thomas Gleixner , Eric Auger Subject: Re: [PATCH 2/3] irqchip/gic-v3: Detect LPI invalidation MMIO registers In-Reply-To: References: <20220315165034.794482-1-maz@kernel.org> <20220315165034.794482-3-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lorenzo.pieralisi@arm.com, linux-kernel@vger.kernel.org, andre.przywara@arm.com, tglx@linutronix.de, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 17 Mar 2022 17:35:23 +0000, Lorenzo Pieralisi wrote: > > On Tue, Mar 15, 2022 at 04:50:33PM +0000, Marc Zyngier wrote: > > Since GICv4.1, an implementation can offer the same MMIO-based > > implementation as DirectLPI, only with an ITS. Given that this > > can be hugely beneficial for workloads that are very LPI masking > > heavy (although these workloads are admitedly a bit odd). > > > > Interestingly, this is independent of RVPEI, which only *implies* > > the functionnality. > > > > So let's detect whether the implementation has GICR_CTLR.IR set, > > and propagate this as DirectLPI to the ITS driver. > > > > Signed-off-by: Marc Zyngier > > --- > > drivers/irqchip/irq-gic-v3.c | 15 +++++++++++---- > > include/linux/irqchip/arm-gic-v3.h | 2 ++ > > 2 files changed, 13 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > > index 736163d36b13..363bfe172033 100644 > > --- a/drivers/irqchip/irq-gic-v3.c > > +++ b/drivers/irqchip/irq-gic-v3.c > > @@ -918,7 +918,11 @@ static int gic_populate_rdist(void) > > static int __gic_update_rdist_properties(struct redist_region *region, > > void __iomem *ptr) > > { > > - u64 typer = gic_read_typer(ptr + GICR_TYPER); > > + u64 typer; > > + u32 ctlr; > > + > > + typer = gic_read_typer(ptr + GICR_TYPER); > > + ctlr = readl_relaxed(ptr + GICR_CTLR); > > > > /* Boot-time cleanip */ > > if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) { > > @@ -941,6 +945,7 @@ static int __gic_update_rdist_properties(struct redist_region *region, > > /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ > > gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); > > gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | > > + !!(ctlr & GICR_CTLR_IR) | > > gic_data.rdists.has_rvpeid); > > gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); > > > > @@ -962,7 +967,11 @@ static void gic_update_rdist_properties(void) > > gic_iterate_rdists(__gic_update_rdist_properties); > > if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) > > gic_data.ppi_nr = 0; > > - pr_info("%d PPIs implemented\n", gic_data.ppi_nr); > > + pr_info("GICv3 features: %d PPIs, %s%s\n", > > + gic_data.ppi_nr, > > + gic_data.has_rss ? "RSS " : "", > > + gic_data.rdists.has_direct_lpi ? "DirectLPI " : ""); > > I understand GICR_CTLR.IR detection (which is v4.1 feature) - I don't No, it is *also* a GICv3 feature. RVPEI implies IR, but IR is a feature on its own (see my reply to Andre on the same subject). Nothing restrict IR to a GICv4.1+ implementation, and KVM is about to expose these registers to the GICv*3* guest. > get why in this patch we are adding a GICv3 DirectLPI info dump (hunk > above), it is probably nitpicking but the hunk above does not seem to > belong in this patch - it is a separate print info refactoring or I am > reading it wrongly. It is indeed just refactoring the kernel messages so that we can see that we enable DirectLPI for GICv3 as well. I honestly don't think this deserves a separate patch. Thanks, M. -- Without deviation from the norm, progress is not possible.