From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D815CC433EF for ; Fri, 4 Mar 2022 16:44:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240752AbiCDQp0 (ORCPT ); Fri, 4 Mar 2022 11:45:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231743AbiCDQpX (ORCPT ); Fri, 4 Mar 2022 11:45:23 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51A581C46B0 for ; Fri, 4 Mar 2022 08:44:36 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D515461DA1 for ; Fri, 4 Mar 2022 16:44:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F1E8C340E9; Fri, 4 Mar 2022 16:44:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1646412275; bh=O/rYuApC0mWYwuhxZoGy9dgi/jdtzvUbyF59nA1gQPw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Hz/roOLF1RLzsMLwHPnGcjc08FiVUts+qgqtIxUGNvM7K5JMBg6L0gU4TydNhqLUU Km9B6kIU6pc/THyWfnATx8vb623YLxtECdDfF6tj1Pao9qBlxYwdn5YyfNM02PDW2Z IGQA7qpyNw9kqGTG7YPmL6b+7eB1jz4bUKwmVdk+SZvJAbXyPKUMTDHhXQ7ajFjwgl Jt38aYCJ1yCzXbKL3GyPYGWIJpX1mptdLPZcUdQz6DdJuqSPKg1XvDakkNK2pwEKHc SCDAqV3zywmoAg40qOMSD765ocaA8DP8MBMnq+x4003pxc68cqh5FceLjFmhigTe/u 4lW/CwgXxXXbg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nQB2e-00CHEk-Tv; Fri, 04 Mar 2022 16:44:33 +0000 Date: Fri, 04 Mar 2022 16:44:32 +0000 Message-ID: <87k0d91xcf.wl-maz@kernel.org> From: Marc Zyngier To: Linu Cherian Cc: "tglx@linutronix.de" , "catalin.marinas@arm.com" , "will@kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linuc.decode@gmail.com" Subject: Re: [EXT] Re: [PATCH V2] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR In-Reply-To: References: <20220304014301.2515-1-lcherian@marvell.com> <87ilsutb6w.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lcherian@marvell.com, tglx@linutronix.de, catalin.marinas@arm.com, will@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuc.decode@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Linu, On Fri, 04 Mar 2022 13:25:42 +0000, Linu Cherian wrote: > > Hi Marc, > > > > static inline u64 gic_read_iar_cavium_thunderx(void) > > > { > > > - u64 irqstat; > > > + u64 irqstat, apr; > > > > > > + apr = read_sysreg_s(SYS_ICC_AP1R0_EL1); > > > > Why only AP1R0? Does the HW only support 5 bits of priority? If it supports > > more, you need to check all the registers that may contain an active priority > > (0xa0 for a standard interrupt, 0x20 for a pNMI). > > > > Yes correct. HW supports only 5 bits of priority groups. > Will note this in the comment. Thanks. > > > > nops(8); > > > irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1); > > > nops(4); > > > mb(); > > > > > > - return irqstat; > > > + if (likely(apr != read_sysreg_s(SYS_ICC_AP1R0_EL1))) > > > + return irqstat; > > > + > > > + return 0x3ff; > > > > This should be ICC_IAR1_EL1_SPURIOUS. > > Looks like we need fixes like below in couple of files to make use > of this macro. > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 5bc01e62c08a..d02b7339d21a 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -18,7 +18,7 @@ > #include > #include > #include > -#include > +#include > > Should I consider fixing these ? > At least its builds fine for me with similar header fixes. Ah, crap. I'd like to avoid dragging too much of the linux/*.h into asm/*.h, as this eventually leads to a pretty terrible mess. Never mind then. I'll look into fixing it independently, and we'll live with the 0x3ff for now. > > > +#define CAVIUM_CPU_PART_THUNDERX_OTX_GEN 0x0A0 > > > > Is this an actual part number? What does 'GEN' stand for? > > > > No, this is not an actual part number. GEN was meant to be generic > to cover a group of part numbers. The problem with that is that it eventually clashes with part numbers that are allocated later, and your old kernel tries to apply a workaround on the new HW... Sticking to the actual parts is a lot safer. Thanks, M. -- Without deviation from the norm, progress is not possible.