From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1424436AbcFMOXu (ORCPT ); Mon, 13 Jun 2016 10:23:50 -0400 Received: from mail2.asahi-net.or.jp ([202.224.39.198]:14277 "EHLO mail2.asahi-net.or.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423255AbcFMOXo (ORCPT ); Mon, 13 Jun 2016 10:23:44 -0400 Date: Mon, 13 Jun 2016 23:23:41 +0900 Message-ID: <87k2htdv6a.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Geert Uytterhoeven Cc: Linux-sh list , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: Re: [PATCH v2 16/17] sh: I/O DATA HDL-U (a.k.a. landisk) Device Tree In-Reply-To: References: <1465714475-24111-1-git-send-email-ysato@users.sourceforge.jp> <1465714475-24111-17-git-send-email-ysato@users.sourceforge.jp> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/24.5 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 13 Jun 2016 17:13:37 +0900, Geert Uytterhoeven wrote: > > Hi Sato-san, > > On Sun, Jun 12, 2016 at 8:54 AM, Yoshinori Sato > wrote: > > --- /dev/null > > +++ b/arch/sh/boot/dts/landisk.dts > > @@ -0,0 +1,150 @@ > > > + pllclk: pllclk { > > + compatible = "renesas,sh7750-pll-clock"; > > + clocks = <&oclk>; > > + #clock-cells = <0>; > > + renesas,mult = <12>; > > + reg = <0xffc00000 2>, <0xffc00008 4>; > > + }; > > + iclk: iclk { > > + compatible = "renesas,sh7750-div-clock"; > > + clocks = <&pllclk>; > > + #clock-cells = <0>; > > + reg = <0xffc00000 2>; > > + renesas,offset = <6>; > > + clock-output-names = "ick"; > > clock-output-names is deprecated for clocks providing a single output. > > > + }; > > + bclk: bclk { > > + compatible = "renesas,sh7750-div-clock"; > > + clocks = <&pllclk>; > > + #clock-cells = <0>; > > + reg = <0xffc00000 2>; > > + renesas,offset = <3>; > > + clock-output-names = "bck"; > > + }; > > + fclk: fclk { > > + compatible = "renesas,sh7750-div-clock"; > > + clocks = <&pllclk>; > > + #clock-cells = <0>; > > + reg = <0xffc00000 2>; > > + renesas,offset = <0>; > > + clock-output-names = "fck"; > > + }; > > I think it will be much easier for maintenance and code reuse to just have a > single "cpg" node that's compatible with "renesas,sh7750-cpg", covering all > CPG registers. Especially since the various clocks use the same registers. > > Cfr. drivers/clk/renesas/cpg-mssr.c. OK. I'll try. > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds -- Yoshinori Sato