From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E7AC18E25 for ; Tue, 18 Mar 2025 22:32:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742337172; cv=none; b=DONzYJeZpGrxd50s60zP7ZJWOSQJHhMN4bG88QSJk8v/aac/Ou9/TpwDVlU1/9WOOmwEMz3LJLQUHpMaj1zmFVI6dbENbz9KffNtfi+xkvmveHh60fIHbRRUcOIvi7tidm3Nz5cmbiUqulAaYHpQGMRlgjt8+YDkt+uenplVydM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742337172; c=relaxed/simple; bh=Zz2IldKLM9Obe+OrFKf035q1HtZbGiurWxoXFchIsvM=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=Dd3JfWzUocUl9mCPPOdJLJFlwHCJurm2eg+ACfSOlPnef03EtjymSpMADjWMc/iS3TMGGh/Bpuq/n4zV8Bs0VdRswmaa+IkBxSWPR+1GyxXjRUbU1hl6HMdArqst83uGVctigTdWRRGJGGdhFDoPT7Aj9fF2N/qQV1SV2DIc9VQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RH+R23br; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RH+R23br" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742337171; x=1773873171; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=Zz2IldKLM9Obe+OrFKf035q1HtZbGiurWxoXFchIsvM=; b=RH+R23brl/uQFVIawRiiHhrRBc7cG8Iahy8MFAO0PKD7lqjaf5s8uFPU u8aQ+/omPb4uqjitawujH7lFhrNhp/Ud8EnYDCmyMF9+H2GncuAbaWnuq wXjU3PayGHpBLhCUOJZS9q4oBeV6fquAECsHRUddKO264ll7miNFRGKVJ +fhZTlpxRBmgoWdke//hJ4VhddDnZyFi2awQV7rh/4MtPq8a6CQ12uSDx IByOvGdU0XlObAgXFIGKYc6yQ/o8ouLqL8aA2KRBrF0I+XGHx6bdYKhSE 0wlhK2Bug3UCoUKH/D/LnLGleOxSIHeMRkEJQFq/v90ZQaBN7A+VJVAye w==; X-CSE-ConnectionGUID: iU7gnUKtRtOIP8rOinBhgA== X-CSE-MsgGUID: pSe/rrnqSCyNYyKVbXhFlg== X-IronPort-AV: E=McAfee;i="6700,10204,11377"; a="53718133" X-IronPort-AV: E=Sophos;i="6.14,258,1736841600"; d="scan'208";a="53718133" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2025 15:32:50 -0700 X-CSE-ConnectionGUID: 3VarUKRaQL2DxkW/3ySj3Q== X-CSE-MsgGUID: ugltZV4CQ/GrJMXqsIfxXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,258,1736841600"; d="scan'208";a="123324307" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.246.228]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2025 15:32:43 -0700 From: Jani Nikula To: Yury Norov , mailhol.vincent@wanadoo.fr Cc: Lucas De Marchi , Rasmus Villemoes , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Simona Vetter , Andrew Morton , linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Andi Shyti , David Laight , Dmitry Baryshkov , Andy Shevchenko Subject: Re: [PATCH v6 4/7] drm/i915: Convert REG_GENMASK*() to fixed-width GENMASK_U*() In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20250308-fixed-type-genmasks-v6-0-f59315e73c29@wanadoo.fr> <20250308-fixed-type-genmasks-v6-4-f59315e73c29@wanadoo.fr> Date: Wed, 19 Mar 2025 00:32:40 +0200 Message-ID: <87ldt2c6lz.fsf@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, 18 Mar 2025, Yury Norov wrote: > On Sat, Mar 08, 2025 at 01:48:51AM +0900, Vincent Mailhol via B4 Relay wrote: >> From: Lucas De Marchi >> >> Now that include/linux/bits.h implements fixed-width GENMASK_U*(), use >> them to implement the i915/xe specific macros. Converting each driver >> to use the generic macros are left for later, when/if other >> driver-specific macros are also generalized. >> >> Signed-off-by: Lucas De Marchi >> Acked-by: Jani Nikula >> Signed-off-by: Vincent Mailhol >> --- >> Changelog: >> >> v5 -> v6: >> >> - No changes. >> >> v4 -> v5: >> >> - Add braket to macro names in patch description, >> e.g. 'REG_GENMASK*' -> 'REG_GENMASK*()' >> >> v3 -> v4: >> >> - Remove the prefixes in macro parameters, >> e.g. 'REG_GENMASK(__high, __low)' -> 'REG_GENMASK(high, low)' >> --- >> drivers/gpu/drm/i915/i915_reg_defs.h | 108 ++++------------------------------- >> 1 file changed, 11 insertions(+), 97 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h >> index e251bcc0c89f5710125bc70f07851b2cb978c89c..39e5ed9511174b8757b9201bff735fa362651b34 100644 >> --- a/drivers/gpu/drm/i915/i915_reg_defs.h >> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h >> @@ -9,76 +9,19 @@ >> #include >> #include >> >> -/** >> - * REG_BIT() - Prepare a u32 bit value >> - * @__n: 0-based bit number >> - * >> - * Local wrapper for BIT() to force u32, with compile time checks. >> - * >> - * @return: Value with bit @__n set. >> +/* >> + * Wrappers over the generic BIT_* and GENMASK_* implementations, >> + * for compatibility reasons with previous implementation >> */ >> -#define REG_BIT(__n) \ >> - ((u32)(BIT(__n) + \ >> - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ >> - ((__n) < 0 || (__n) > 31)))) >> +#define REG_GENMASK(high, low) GENMASK_U32(high, low) >> +#define REG_GENMASK64(high, low) GENMASK_U64(high, low) >> +#define REG_GENMASK16(high, low) GENMASK_U16(high, low) >> +#define REG_GENMASK8(high, low) GENMASK_U8(high, low) > > Nit. Maybe just > > #define REG_GENMASK GENMASK_U32 Please just keep it as it is for clarity. BR, Jani. -- Jani Nikula, Intel