From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D9341FB4 for ; Mon, 23 Dec 2024 19:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734980489; cv=none; b=smTeySNR01PNpflCjwiw5sRP0yDfSy9V8ckuWhPs2OHDamI9GrU0H6NutuH1DJNDKviYg5JcPrMOl9IVFzh4ZOcSZCN3e0TqHMqG8ibruCYBT4OWVzo7/pI0VJ00Z42OJlwcebDMHXTHeqLBVkX9xW0/x7LuTYoYbw5dZWaIvOo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734980489; c=relaxed/simple; bh=dOIDsBuhIWYlOhDYObmF/pMoCGKUr2mxtjBccWWB15o=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=f8ZRxStFgM47qGuoYxGHVWQZ/IC3JMh9LVkd6hgjAobIivzLHeXEkXfnc+yVmvuADse7Tg2Y5Qn9utwhrwOMFxGNh42PsCZ+9bKnbpuIUnZ+mIC44aS9/uyKF7lEkRCXtAPEwZhe6l3d5fvU9bfWj/M1chs+aXEonizphEMdVR8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=CFJbPtft; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="CFJbPtft" Received: by mail.gandi.net (Postfix) with ESMTPSA id 91D88FF803; Mon, 23 Dec 2024 19:01:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1734980485; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dOIDsBuhIWYlOhDYObmF/pMoCGKUr2mxtjBccWWB15o=; b=CFJbPtft1cAi9gS1bNfPVvlq9d4TDktlA+P1LY0XAT1JHdKwdvjPEWP8zaOhDBXjx2fSSE HbeqSYQo05AL4bKiNURxm5HAGvle/LbXOn3QOBR1gOTyj7y5sRGwykJyf0NhErxZoI7oRP 1bSg+KCtz3AVQW/hXDmBt3tiuqRgYMkX9yTzNPSEA/A7sCBN0KivK/4O8eqsW777/wKVih TbsVPGp81gQovTTSWKlxbZdNY0cGoGJyBcsZLUULpab1XYeMsntMnZxsNh720yExDzJyOa MqeaKBcnmk3cmHuEKHfbmum8dl8xjsBuNf9bA5FtwZJ3syCRj8PfX8TyAT7CIg== From: Miquel Raynal To: Martin Kepplinger Cc: Nikolaus Voss , Alexander Stein , Liu Ying , Luca Ceresoli , Fabio Estevam , Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , nikolaus.voss@haag-streit.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4] drm: bridge: fsl-ldb: fixup mode on freq mismatch In-Reply-To: <80cdb6d83f37c1c87a71ad567b2c4f2433219465.camel@posteo.de> (Martin Kepplinger's message of "Thu, 19 Dec 2024 12:39:05 +0000") References: <20241219105416.4AE0D1201@mail.steuer-voss.de> <80cdb6d83f37c1c87a71ad567b2c4f2433219465.camel@posteo.de> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Mon, 23 Dec 2024 20:01:22 +0100 Message-ID: <87ldw6rzp9.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com Hello Martin, On 19/12/2024 at 12:39:05 GMT, Martin Kepplinger wrote: > Am Donnerstag, dem 19.12.2024 um 11:54 +0100 schrieb Nikolaus Voss: >> LDB clock has to be a fixed multiple of the pixel clock. >> Although LDB and pixel clock have a common source, this >> constraint cannot be satisfied for any pixel clock at a >> fixed source clock. >>=20 >> Violating this constraint leads to flickering and distorted >> lines on the attached display. >>=20 >> To overcome this, there are these approches: >>=20 >> 1. Modify the base PLL clock statically by changing the >> =C2=A0=C2=A0 device tree, implies calculating the PLL clock by >> =C2=A0=C2=A0 hand, e.g. commit 4fbb73416b10 ("arm64: dts: >> =C2=A0=C2=A0 imx8mp-phyboard-pollux: Set Video PLL1 frequency to 506.8 M= Hz") >>=20 >> 2. Walk down the clock tree and modify the source clock. >> =C2=A0=C2=A0 Proposed patch series by Miquel Raynal: >> =C2=A0=C2=A0 [PATCH 0/5] clk: Fix simple video pipelines on i.MX8 >>=20 >> 3. This patch: check constraint violation in >> =C2=A0=C2=A0 drm_bridge_funcs.atomic_check() and adapt the pixel >> =C2=A0=C2=A0 clock in drm_display_mode.adjusted_mode accordingly. >>=20 >> Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale >> i.MX8MP LDB bridge") >> Cc: # 6.12.x, 6.6.x >> Signed-off-by: Nikolaus Voss >>=20 >> --- I didn't investigate further, but FYI this approach does not fix my situation with iMX8MP. I am not saying it's wrong, because I am not experienced enough with drm, but at least that it is not a replacement of point #2 above. Cheers, Miqu=C3=A8l