From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 537EFC433FE for ; Thu, 24 Nov 2022 09:10:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229828AbiKXJKx (ORCPT ); Thu, 24 Nov 2022 04:10:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229812AbiKXJKo (ORCPT ); Thu, 24 Nov 2022 04:10:44 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27B00114BB8; Thu, 24 Nov 2022 01:10:43 -0800 (PST) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669281041; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wxDUIdcZqV8qzd3zeBKegPzdz1xDmsJGqZx6pnAnrGQ=; b=k3TAhx0ejLrT/moxsbfBhl8aA+yL/nIzDsmPXXG0r5Q1a91rSr0UtC/Urqx2ObJb8XI7Pu B4s/8kuWBUqqBgK67MLP8zwvpH3PH1wJiT+lp/D0avGZciW4WS2R/4llHDOsJUCLIenTDE KllfQYTa1vbt0SwcnX/A6++E/m3izy+6ZJJt4hp5QecW7n3xc8bLXrxW741G3uGYt1mV9O vULPdTh5H7A/B19Qx/tVOagL0ML0lgo/5/LxaAFHnVeUz3BfkLQPBvtlf8WcWZ2KjbzS8W P0DNzdADWLHJ2PAVMOMWnyMN+Ph/0QyM3uWJZtKeOpKQEMapNdoTzloA97DoEw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669281041; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wxDUIdcZqV8qzd3zeBKegPzdz1xDmsJGqZx6pnAnrGQ=; b=H64hB/MybL/Y4njxJn6/CNrDc6lNjcLNNpfUi4NJ9+K+QCU6VdjV/8vDRHLiXGUgpl+J0H AOuaR6JsRJnchcCQ== To: "Tian, Kevin" , LKML Cc: "x86@kernel.org" , Joerg Roedel , Will Deacon , "linux-pci@vger.kernel.org" , Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , "Jiang, Dave" , Alex Williamson , "Williams, Dan J" , Logan Gunthorpe , "Raj, Ashok" , Jon Mason , Allen Hubbe Subject: RE: [patch V2 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support In-Reply-To: References: <20221121083657.157152924@linutronix.de> <20221121091328.026206487@linutronix.de> Date: Thu, 24 Nov 2022 10:10:41 +0100 Message-ID: <87leo0d8fi.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 24 2022 at 03:10, Kevin Tian wrote: >> From: Thomas Gleixner >> Sent: Monday, November 21, 2022 10:38 PM >> >> The IMS domains have a few constraints: >> >> - The index space is managed by the core code. >> >> Device memory based IMS provides a storage array with a fixed size >> which obviously requires an index. But there is no association between >> index and functionality so the core can randomly allocate an index in >> the array. >> >> Queue memory based IMS does not have the concept of an index as the >> storage is somewhere in memory. In that case the index is purely >> software based to keep track of the allocations. > > 'Queue' could be a HW queue or SW queue. Is it clearer to just use > 'system memory based IMS" here? Yes