From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1BE1C433EF for ; Sat, 16 Jul 2022 18:40:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231998AbiGPSkA (ORCPT ); Sat, 16 Jul 2022 14:40:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229558AbiGPSj5 (ORCPT ); Sat, 16 Jul 2022 14:39:57 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C09311F4 for ; Sat, 16 Jul 2022 11:39:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 77FB8B80CB1 for ; Sat, 16 Jul 2022 18:39:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 01CE9C34114; Sat, 16 Jul 2022 18:39:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657996794; bh=jHD1xGVxd+hAY4K3c4gWTjcSl0wcbkWVstMVctO5jc8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=E36SIMXrsVUJVvtJDnLBtfkG/YAefrt81suS7zC1xBbj5L39HlIZADJ/elBxGe0Oe VwaZjWuPmMo1V2R1wTnAR326IIQ4C6k9AgGURirNiNZ8jeBE1mQz6lC+cn7MQX3j5M NddcgWmH7HHZoRVILTqyCnQPDPfXGT6vjshyy2JVtqEoqvCuAqzAZWwD4aAlvfGh2c wzUOnMla/bA6tevi4O1BFBni0YGBzgL70jy+IpbprGeF7gZuXDcHXbvWCmg+v4SWdv msBFX4sLQsQX22dLKPlpP++SMQWZVe1caA77rCtfTKJra33ZcmrvL4zGccEMUhf5AA L+nCly2nNLntw== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oCmhj-007uJh-Lx; Sat, 16 Jul 2022 19:39:51 +0100 Date: Sat, 16 Jul 2022 19:39:46 +0100 Message-ID: <87less52bx.wl-maz@kernel.org> From: Marc Zyngier To: Jianmin Lv Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Hanjun Guo , Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen Subject: Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers In-Reply-To: <1657868751-30444-1-git-send-email-lvjianmin@loongson.cn> References: <1657868751-30444-1-git-send-email-lvjianmin@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: lvjianmin@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, guohanjun@huawei.com, lorenzo.pieralisi@arm.com, jiaxun.yang@flygoat.com, chenhuacai@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 15 Jul 2022 08:05:36 +0100, Jianmin Lv wrote: > > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. > LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit > version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its > boot protocol LoongArch-specific interrupt controllers (similar to APIC) > are already added in the ACPI Specification 6.5(which may be published in > early June this year and the board is reviewing the draft). > > Currently, LoongArch based processors (e.g. Loongson-3A5000) can only > work together with LS7A chipsets. The irq chips in LoongArch computers > include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O > Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), > HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main > Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller > in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). [...] Compiling this series for loongarch with loongson3_defconfig on top of 5.19-rc3 results in the following: loongarch64-linux-ld: drivers/irqchip/irq-loongson-eiointc.o: in function `.L60': irq-loongson-eiointc.c:(.init.text+0x4c): undefined reference to `pch_msi_acpi_init' loongarch64-linux-ld: drivers/irqchip/irq-loongson-htvec.o: in function `pch_msi_parse_madt': irq-loongson-htvec.c:(.init.text+0x14): undefined reference to `pch_msi_acpi_init' make: *** [Makefile:1164: vmlinux] Error 1 I *really* would have expected this series to be in a better shape after over 15 rounds, but it looks like I'm expecting too much. I haven't investigated the breakage, but this should (at the very least) pass the defconfig test and optional drivers not being selected. The corresponding MIPS configuration seems to build fine. M. -- Without deviation from the norm, progress is not possible.