From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B0803FDC08 for ; Fri, 26 Jun 2026 14:49:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782485379; cv=none; b=JzCRUZWMmeeYJz0Ud+UQhpZfUX7tSi3S8dB69oPpEmcYFsx0ZfWcKLpJSmqLquh1mGyqSHE5n5ZsHtX84ljDPBtcdl37StnUzflbv/ngMerC0PehJ1uDDL9oFPwHZo+bQ5GKuuLvwx+xwT74VSlJVHszh/s9fy0Tdto/dVnm7SA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782485379; c=relaxed/simple; bh=3cKUEsaAyFJsxmKS4IlA8CiEg6NOg3KKa0qFDE6BRcY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=OOq21cwFuouViQmgMLt8thgqRcedHliAeo6vNCNLOkTPvmTFtSjQOH8A3D6EvsXHrcbo1hXjQk2Qsk/iW0qp3uQF6CopoZwMTY2LyGOoPFd+y/xpQlpl4vtAYavipPD7FEJBEfvow2r6c7GJLSA/X4W781AtEKQdMOl54gW8i64= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l96QXfT0; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l96QXfT0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D87771F000E9; Fri, 26 Jun 2026 14:49:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1782485376; bh=MajDZZsdxVv5j8j0AkZZeULoFyBhiZQV65n6q/Aibfo=; h=From:To:Cc:Subject:In-Reply-To:References:Date; b=l96QXfT0MVBbF8iEAEpnd77ZR0hc5ovggbWBjyhINtDvy/5eY6s+KkwNds5c8nBZr xtNlX1nYa2G4Wjp5Ue/Yg86jTx05sIaP978Q10qYCHNfTpPeVbcn/1dN4upRD8uZWp mN5nJ8Fm8lo/jONNbzUgk0FhtcC+QgNAtwAAhBBB+wIKoNIFCXaBJcHJws5/Ct9vj8 OBUYPyHZPP9Be3KNOUWu+HD3GY8568mdoD4OBQMmE+PatltcES6ZU/4h1Z+QnL3XvU yhgs2xQ8ByzB9MuuMesk/0ss3aRJSSTROI1m2Uv+Kx1BedXyQHxRjYmiVs8iEiuscu Zx8s0CziHllbQ== From: Thomas Gleixner To: Chuyi Zhou , mingo@redhat.com, luto@kernel.org, peterz@infradead.org, paulmck@kernel.org, muchun.song@linux.dev, bp@alien8.de, dave.hansen@linux.intel.com, pbonzini@redhat.com, bigeasy@linutronix.de, clrkwllms@kernel.org, rostedt@goodmis.org, nadav.amit@gmail.com, vkuznets@redhat.com Cc: linux-kernel@vger.kernel.org, Chuyi Zhou Subject: Re: [PATCH v8 11/14] x86/mm: Cap flush_tlb_info alignment at 64 bytes In-Reply-To: <20260616111127.966468-12-zhouchuyi@bytedance.com> References: <20260616111127.966468-1-zhouchuyi@bytedance.com> <20260616111127.966468-12-zhouchuyi@bytedance.com> Date: Fri, 26 Jun 2026 16:49:33 +0200 Message-ID: <87mrwhicg2.ffs@fw13> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, Jun 16 2026 at 19:11, Chuyi Zhou wrote: > A stack allocated flush_tlb_info should keep cacheline alignment to > avoid the regression that motivated the per-CPU storage, but using > SMP_CACHE_BYTES directly can make the stack frame grow excessively on > configurations with large cache lines[1]. > > Add FLUSH_TLB_INFO_ALIGN and cap the type alignment at 64 bytes. The > existing per-CPU flush_tlb_info instance remains > DEFINE_PER_CPU_SHARED_ALIGNED(), so its per-CPU shared-cacheline > alignment is unchanged. > > The capped type alignment matters once flush_tlb_info is moved back to the > stack by the next patch. This prepares for moving it back to the stack .... > link[1]: https://lore.kernel.org/all/tip-780e0106d468a2962b16b52fdf42898f2639e0a0@git.kernel.org/ This is not a documented tag. Please don't invent random tags just because. Aside of that this lore link is silly. What's wrong with referencing the commit? .. excessively on configurations with large cache lines, which was addressed in commit 780e0106d4 "....". Hmm? > Signed-off-by: Chuyi Zhou > --- > arch/x86/include/asm/tlbflush.h | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h > index 0545fe75c3fa..5889a6c4e956 100644 > --- a/arch/x86/include/asm/tlbflush.h > +++ b/arch/x86/include/asm/tlbflush.h > @@ -4,6 +4,7 @@ > > #include > #include > +#include > #include > > #include > @@ -211,6 +212,8 @@ extern u16 invlpgb_count_max; > > extern void initialize_tlbstate_and_flush(void); > > +#define FLUSH_TLB_INFO_ALIGN MIN(SMP_CACHE_BYTES, 64) This wants a comment. > /* > * TLB flushing: > * > @@ -249,7 +252,7 @@ struct flush_tlb_info { > u8 stride_shift; > u8 freed_tables; > u8 trim_cpumask; > -}; > +} __aligned(FLUSH_TLB_INFO_ALIGN); > > void flush_tlb_local(void); > void flush_tlb_one_user(unsigned long addr);