From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A28423507B for ; Fri, 20 Mar 2026 12:48:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774010898; cv=none; b=YzqTSg/ztjfsIe+InOhMnuPE/lRu2hR+QkbTJdT42zQY2skke+hIFiusVd7hVP/2bQXVQGdxY91R2OPmHtedtkJlj5iqtMUgw4NaPZ7QU6aQ50FriFK3spdfmDZjmqyhlwphIBZkartAJTFz+NoU4+lGE3dTF+06FDsQENguqw4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774010898; c=relaxed/simple; bh=AUaddx7duKOZF74vxsjQdmRGibJucaPVn0EGOs8rrMU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=d4kk5YxFs3dS4Xu7DIqcntXa/8asaa88QM7TI5xHLD1FAkoGosDE3B+5OVhK965UV2hmPenEOxhPDnUlOGOSEw2zCzuDaQy63CfonV/ot895B5pxpzoGmdoniNg+rQEUsc5gXRYSt1Bx/YAUsRlvkxuN1Kbke62AOvI6y+XoRSQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lH/Dijs4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lH/Dijs4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D3F32C19425; Fri, 20 Mar 2026 12:48:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774010898; bh=AUaddx7duKOZF74vxsjQdmRGibJucaPVn0EGOs8rrMU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=lH/Dijs4mUHx4a+fKM6/ZsfeMcFIqOTrBetU8l9qlMkr3fk0l8O2LissFPZnUgjaC Wv3mhst+jGXepVPi05KrKAHFtF0nRdtvcXcvHyY+uFeRF4LcfMRKMgXd+xadTb4vSv Z5Imy9Njs00RUPq33G6ezgGzJZH1qC5H0oDk2obCei3QbGPCM4Xl7mrZ90FD1rSMow vinUyVAp4P7vzB+j3+rYquB2iz4ua5PKFjdAc7osWimtqTrim4CY2CKXCTM3+7XY9y VpZVzXF0ZFzZHPpoWqcfIvUnTZf5Al8jHa88JHeuG0EnpOVR9ZNXz2Cvo7YQMCUY8J i6kpmJzL10eqQ== From: Thomas Gleixner To: Uros Bizjak Cc: LKML , Mathieu Desnoyers , =?utf-8?Q?Andr=C3=A9?= Almeida , Sebastian Andrzej Siewior , Carlos O'Donell , Peter Zijlstra , Florian Weimer , Rich Felker , Torvald Riegel , Darren Hart , Ingo Molnar , Davidlohr Bueso , Arnd Bergmann , "Liam R . Howlett" , Thomas =?utf-8?Q?Wei=C3=9Fschuh?= Subject: Re: [patch v2 11/11] x86/vdso: Implement __vdso_futex_robust_try_unlock() In-Reply-To: References: <20260319225224.853416463@kernel.org> <20260319231239.882002347@kernel.org> Date: Fri, 20 Mar 2026 13:48:14 +0100 Message-ID: <87ms02k6pd.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Mar 20 2026 at 08:14, Uros Bizjak wrote: > On Fri, Mar 20, 2026 at 12:25=E2=80=AFAM Thomas Gleixner wrote: >> + [zero] "S" (0UL) \ > > [zero] represents an internal register, so the above constraint can be > "r" (*). If it remains a hard register constraint (%rsi) for some > reason then the above two comments should be updated to reflect the > new constraint. Right. That's a leftover from some earlier experiment where I needed the 'zero' register at a fixed place, but that's all gone. > With the constraint changed to "r": > > Acked-by: Uros Bizjak (for asm template) > > (*) "r" allows the compiler some more freedom. The compiler tracks the > values in registers, so it can reuse zero from an unrelated register > without moving it to the %rsi and without clobbering the source > register. In non-trivial functions, there is a high chance that needed > value is already available in some register. I'm aware of that. Thanks, tglx