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From: Thomas Gleixner <tglx@linutronix.de>
To: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>, linux-kernel@vger.kernel.org
Cc: bp@alien8.de, mingo@redhat.com, dave.hansen@linux.intel.com,
	Thomas.Lendacky@amd.com, nikunj@amd.com, Santosh.Shukla@amd.com,
	Vasant.Hegde@amd.com, Suravee.Suthikulpanit@amd.com,
	David.Kaplan@amd.com, x86@kernel.org, hpa@zytor.com,
	peterz@infradead.org, seanjc@google.com, pbonzini@redhat.com,
	kvm@vger.kernel.org, kirill.shutemov@linux.intel.com,
	huibo.wang@amd.com, naveen.rao@amd.com
Subject: Re: [RFC v2 04/17] x86/apic: Initialize APIC ID for Secure AVIC
Date: Fri, 21 Mar 2025 14:52:43 +0100	[thread overview]
Message-ID: <87msde32z8.ffs@tglx> (raw)
In-Reply-To: <20250226090525.231882-5-Neeraj.Upadhyay@amd.com>

On Wed, Feb 26 2025 at 14:35, Neeraj Upadhyay wrote:
> Initialize the APIC ID in the Secure AVIC APIC backing page with
> the APIC_ID msr value read from Hypervisor. Maintain a hashmap to
> check and report same APIC_ID value returned by Hypervisor for two
> different vCPUs.

What for?
 
> +struct apic_id_node {
> +	 struct llist_node node;
> +	 u32 apic_id;
> +	 int cpu;
> +};

https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers

and please read the rest of the document too.

> +static void init_backing_page(void *backing_page)
> +{
> +	struct apic_id_node *next_node, *this_cpu_node;
> +	unsigned int apic_map_slot;
> +	u32 apic_id;
> +	int cpu;
> +
> +	/*
> +	 * Before Secure AVIC is enabled, APIC msr reads are
> +	 * intercepted. APIC_ID msr read returns the value
> +	 * from hv.

Can you please write things out? i.e. s/hv/hypervisor/ This is not twatter.

> +	 */
> +	apic_id = native_apic_msr_read(APIC_ID);
> +	set_reg(backing_page, APIC_ID, apic_id);
> +
> +	if (!apic_id_map)
> +		return;
> +
> +	cpu = smp_processor_id();
> +	this_cpu_node = &per_cpu(apic_id_node, cpu);
> +	this_cpu_node->apic_id = apic_id;
> +	this_cpu_node->cpu = cpu;
> +	/*
> +	 * In common case, apic_ids for CPUs are sequentially numbered.
> +	 * So, each CPU should hash to a different slot in the apic id
> +	 * map.
> +	 */
> +	apic_map_slot = apic_id % nr_cpu_ids;
> +	llist_add(&this_cpu_node->node, &apic_id_map[apic_map_slot]);

Why does this need to be a llist? What's wrong about a trivial hlist?

> +	/* Each CPU checks only its next nodes for duplicates. */
> +	llist_for_each_entry(next_node, this_cpu_node->node.next, node) {
> +		if (WARN_ONCE(next_node->apic_id == apic_id,
> +			      "Duplicate APIC %u for cpu %d and cpu %d. IPI handling will suffer!",
> +			      apic_id, cpu, next_node->cpu))
> +			break;
> +	}

This does not make any sense at all. The warning is completely useless
because two milliseconds later the topology evaluation code will yell
about mismatch of APIC IDs and catch the duplicate.

So what is this overengineered thing buying you? Just more
incomprehensible security voodoo for no value.

Thanks,

        tglx

  reply	other threads:[~2025-03-21 13:52 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-26  9:05 [RFC v2 00/17] AMD: Add Secure AVIC Guest Support Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 01/17] x86/apic: Add new driver for Secure AVIC Neeraj Upadhyay
2025-03-20 15:51   ` Borislav Petkov
2025-03-21  3:44     ` Neeraj Upadhyay
2025-03-21 13:55       ` Borislav Petkov
2025-03-21 16:09         ` Neeraj Upadhyay
2025-03-21 17:11           ` Borislav Petkov
2025-04-01  5:12             ` Neeraj Upadhyay
2025-04-02  9:47               ` Borislav Petkov
2025-04-02 10:34                 ` Neeraj Upadhyay
2025-04-07 13:17                   ` Borislav Petkov
2025-04-07 16:17                     ` Neeraj Upadhyay
2025-03-21 12:44     ` Thomas Gleixner
2025-03-21 13:52       ` Borislav Petkov
2025-03-21 12:53   ` Thomas Gleixner
2025-03-21 13:25     ` Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 02/17] x86/apic: Initialize Secure AVIC APIC backing page Neeraj Upadhyay
2025-03-21 13:08   ` Thomas Gleixner
2025-03-21 13:49     ` Neeraj Upadhyay
2025-03-21 16:32   ` Francesco Lavra
2025-03-21 17:00     ` Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 03/17] x86/apic: Populate .read()/.write() callbacks of Secure AVIC driver Neeraj Upadhyay
2025-03-21 13:38   ` Thomas Gleixner
2025-03-21 14:00     ` Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 04/17] x86/apic: Initialize APIC ID for Secure AVIC Neeraj Upadhyay
2025-03-21 13:52   ` Thomas Gleixner [this message]
2025-03-21 15:11     ` Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 05/17] x86/apic: Add update_vector callback " Neeraj Upadhyay
2025-03-21 14:27   ` Thomas Gleixner
2025-03-21 15:35     ` Neeraj Upadhyay
2025-03-25 12:10       ` Neeraj Upadhyay
2025-03-27 10:27         ` Thomas Gleixner
2025-03-27 11:17           ` Neeraj Upadhyay
2025-03-27 12:18             ` Thomas Gleixner
2025-03-27 12:30               ` Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 06/17] x86/apic: Add support to send IPI " Neeraj Upadhyay
2025-03-21 15:06   ` Thomas Gleixner
2025-04-01 10:25     ` Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 07/17] x86/apic: Support LAPIC timer " Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 08/17] x86/sev: Initialize VGIF for secondary VCPUs " Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 09/17] x86/apic: Add support to send NMI IPI " Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 10/17] x86/apic: Allow NMI to be injected from hypervisor " Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 11/17] x86/sev: Enable NMI support " Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 12/17] x86/apic: Read and write LVT* APIC registers from HV for SAVIC guests Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 13/17] x86/apic: Handle EOI writes " Neeraj Upadhyay
2025-03-21 15:41   ` Thomas Gleixner
2025-03-21 17:11     ` Sean Christopherson
2025-03-27 10:48       ` Thomas Gleixner
2025-03-27 12:20         ` Thomas Gleixner
2025-03-27 14:19           ` Sean Christopherson
2025-03-27 16:54             ` Thomas Gleixner
2025-02-26  9:05 ` [RFC v2 14/17] x86/apic: Add kexec support for Secure AVIC Neeraj Upadhyay
2025-03-21 15:48   ` Thomas Gleixner
2025-04-01 10:35     ` Neeraj Upadhyay
2025-04-01 18:31       ` Thomas Gleixner
2025-04-02  2:40         ` Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 15/17] x86/apic: Enable Secure AVIC in Control MSR Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 16/17] x86/sev: Prevent SECURE_AVIC_CONTROL MSR interception for Secure AVIC guests Neeraj Upadhyay
2025-02-26  9:05 ` [RFC v2 17/17] x86/sev: Indicate SEV-SNP guest supports Secure AVIC Neeraj Upadhyay

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