From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90691A59 for ; Tue, 28 Jan 2025 08:34:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738053294; cv=none; b=ZGBGAmzkAua5sIKqzqvWDIv9UpwprEQTEJUO33rA+Hz1sZJ2m0ktcBCGJPUXUwWqm6hKb2de4GmqN4TdpThmrvR037MTg0GrqwUlfyiaPLUD4BlKVQgcCtpPuKngqk3/4Mk5USIMJCDCb/Rgn05i7qUdEs4mV7vlVvggt8aVUus= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738053294; c=relaxed/simple; bh=WNneNe6kJKss9QO+jmHx6Hy+8bI9wVL2Ho5u/+oOu+g=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=a+SfMLmCCiNaZ9FP/rqazB/k7cSFx3ghK5bYnCGIyvpbdF2dKwLkDbQqidgiEo9/Nrdwyrh7S+d9EWYRFkmr1Bp15XUeYse5zKwUbSYH1Up7Lh0QG7Ehx+skgATgPAPwMxLP3XhTHTCcgZ7xB4i6MNPgEk3nicMNgzeizU4BJBg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LFqkEsqH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LFqkEsqH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E27FDC4CEE1; Tue, 28 Jan 2025 08:34:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738053294; bh=WNneNe6kJKss9QO+jmHx6Hy+8bI9wVL2Ho5u/+oOu+g=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=LFqkEsqHz//qHlrU5FmUzatieAa1oI9pJpGSEAzlsJWSZynnK93P1KXuEL0COqFFp 2tr5zTXme8UrD09T+vkDvdrrZLn7Wj2hJ/jrcypyZv3Ctyy5fJjZcS9I83B3YMMsJ2 8YxzwnJKmg97X8hZBGMjgdFIpDNyE0QGVM91447EVnFSfzgjwCpGHYJ1rlHYMatWrT vj3qFx6QRdNFg4MRLNla7Bbp1pSuCtsYV/xdd0+MnYrvTQ5FZJ0g8fwYaleZ26voRO xpvK+4iwwtvU2oPqsO5pgb3ze0Hbozgx8RoBNbZF1gpK7+NzUNdyLHaPe3jJoLFfrM BKQnaGMPCp3mA== Received: from 82-132-233-27.dab.02.net ([82.132.233.27] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tch3b-00FzQg-9z; Tue, 28 Jan 2025 08:34:51 +0000 Date: Tue, 28 Jan 2025 08:34:47 +0000 Message-ID: <87msfbtjyw.wl-maz@kernel.org> From: Marc Zyngier To: Zaid Alali Cc: catalin.marinas@arm.com, will@kernel.org, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, mark.rutland@arm.com, ruanjinjie@huawei.com, oliver.upton@linux.dev, robh@kernel.org, anshuman.khandual@arm.com, james.morse@arm.com, shiqiliu@hust.edu.cn, eahariha@linux.microsoft.com, scott@os.amperecomputing.com, joey.gouly@arm.com, ardb@kernel.org, yangyicong@hisilicon.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: errata: Add Ampere erratum AC04_CPU_50 workaround alternative In-Reply-To: <20250127201829.209258-1-zaidal@os.amperecomputing.com> References: <20250127201829.209258-1-zaidal@os.amperecomputing.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 82.132.233.27 X-SA-Exim-Rcpt-To: zaidal@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, mark.rutland@arm.com, ruanjinjie@huawei.com, oliver.upton@linux.dev, robh@kernel.org, anshuman.khandual@arm.com, james.morse@arm.com, shiqiliu@hust.edu.cn, eahariha@linux.microsoft.com, scott@os.amperecomputing.com, joey.gouly@arm.com, ardb@kernel.org, yangyicong@hisilicon.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 27 Jan 2025 20:18:29 +0000, Zaid Alali wrote: > > Add an alternative code sequence to work around Ampere erratum > AC03_CPU_50 on AmpereOne and Ampere1A. > > Due to AC03_CPU_50, when ICC_PMR_EL1 should have a value of 0xf0 a > direct read of the register will return a value of 0xf8. An incorrect > value from a direct read can only happen with the value 0xf0. Under which precise conditions? Does it equally apply to virtual interrupts or SCR_EL3.FIQ==0, for which there is no non-secure shift (which I can only assume is the source of the erratum)? Does it equally affect G0 and G1 interrupts? > > Note: Currently there are no checks against a value of 0xf0, and that > save restore of 0xf8 -> 0xf0 is fine, so this is all future proofing. > > Signed-off-by: Zaid Alali > --- > arch/arm64/Kconfig | 16 ++++++++++++++++ > arch/arm64/include/asm/arch_gicv3.h | 2 +- > arch/arm64/include/asm/daifflags.h | 4 ++-- > arch/arm64/include/asm/irqflags.h | 6 +++--- > arch/arm64/include/asm/sysreg.h | 9 +++++++++ > arch/arm64/kernel/cpu_errata.c | 15 +++++++++++++++ > arch/arm64/kernel/entry.S | 4 ++++ > arch/arm64/tools/cpucaps | 1 + Please add an entry to Documentation/arch/arm64/silicon-errata.txt. > 8 files changed, 51 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index fcdd0ed3eca8..8d6e263d66c7 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -461,6 +461,22 @@ config AMPERE_ERRATUM_AC03_CPU_38 > > If unsure, say Y. > > +config AMPERE_ERRATUM_AC03_CPU_50 > + bool "AmpereOne: AC03_CPU_50: Certain checks for ICC_PMR_EL1 that expects the value 0xf0 may read 0xf8 instead" > + default y > + help > + This option adds an alternative code sequence to work around Ampere > + erratum AC03_CPU_50 on AmpereOne and Ampere1A. > + > + Due to AC03_CPU_50, when ICC_PMR_EL1 should have a value of 0xf0 a > + direct read of the register will return a value of 0xf8. An incorrect > + value from a direct read can only happen with the value 0xf0. > + > + The workaround for the erratum will do logical AND 0xf0 to the > + value read from ICC_PMR_EL1 register before returning the value. > + > + If unsure, say Y. > + An alternative for this would simply to prevent the enabling of pNMI on this platform. M. -- Without deviation from the norm, progress is not possible.