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X-CSE-ConnectionGUID: jpi/7am/RHqd5WdSn11wgQ== X-CSE-MsgGUID: gv9I8kefQoSTOOxia6QhNA== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="40844920" X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="40844920" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 02:22:25 -0700 X-CSE-ConnectionGUID: D+IpKCtRTomwlwGuBOc3FQ== X-CSE-MsgGUID: y8duOdhSQS2qYZJsphVRQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,249,1725346800"; d="scan'208";a="87508070" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.246.234]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2024 02:22:16 -0700 From: Jani Nikula To: imre.deak@intel.com, Abel Vesa Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Karol Herbst , Lyude Paul , Danilo Krummrich , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Bjorn Andersson , Konrad Dybcio , Johan Hovold , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH RFC 1/4] drm/dp: Add helper to set LTTPRs in transparent mode In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20241031-drm-dp-msm-add-lttpr-transparent-mode-set-v1-0-cafbb9855f40@linaro.org> <20241031-drm-dp-msm-add-lttpr-transparent-mode-set-v1-1-cafbb9855f40@linaro.org> Date: Fri, 01 Nov 2024 11:22:13 +0200 Message-ID: <87msijjol6.fsf@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Thu, 31 Oct 2024, Imre Deak wrote: > On Thu, Oct 31, 2024 at 05:12:45PM +0200, Abel Vesa wrote: >> According to the DisplayPort standard, LTTPRs have two operating >> modes: >> - non-transparent - it replies to DPCD LTTPR field specific AUX >> requests, while passes through all other AUX requests >> - transparent - it passes through all AUX requests. >> >> Switching between this two modes is done by the DPTX by issuing >> an AUX write to the DPCD PHY_REPEATER_MODE register. >> >> Add a generic helper that allows switching between these modes. >> >> Signed-off-by: Abel Vesa >> --- >> drivers/gpu/drm/display/drm_dp_helper.c | 17 +++++++++++++++++ >> include/drm/display/drm_dp_helper.h | 1 + >> 2 files changed, 18 insertions(+) >> >> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c >> index 6ee51003de3ce616c3a52653c2f1979ad7658e21..38d612345986ad54b42228902ea718a089d169c4 100644 >> --- a/drivers/gpu/drm/display/drm_dp_helper.c >> +++ b/drivers/gpu/drm/display/drm_dp_helper.c >> @@ -2694,6 +2694,23 @@ int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) >> } >> EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); >> >> +/** >> + * drm_dp_lttpr_set_transparent_mode - set the LTTPR in transparent mode >> + * @aux: DisplayPort AUX channel >> + * @enable: Enable or disable transparent mode >> + * >> + * Returns 0 on success or a negative error code on failure. > > Should be "Returns 1 on success". But is that a sensible return value? > >> + */ >> + Superfluous newline. >> +int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable) >> +{ >> + u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : >> + DP_PHY_REPEATER_MODE_NON_TRANSPARENT; >> + >> + return drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, val); >> +} >> +EXPORT_SYMBOL(drm_dp_lttpr_set_transparent_mode); >> + >> /** >> * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs >> * @caps: LTTPR common capabilities >> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h >> index 279624833ea9259809428162f4e845654359f8c9..8821ab2d36b0e04d38ccbdddcb703b34de7ed680 100644 >> --- a/include/drm/display/drm_dp_helper.h >> +++ b/include/drm/display/drm_dp_helper.h >> @@ -625,6 +625,7 @@ int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, >> u8 caps[DP_LTTPR_PHY_CAP_SIZE]); >> int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); >> int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); >> +int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable); >> int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); >> bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); >> bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); >> >> -- >> 2.34.1 >> -- Jani Nikula, Intel