From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAAC1186E48; Mon, 26 Aug 2024 15:25:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724685938; cv=none; b=j+KcWFuSOgDK02k71jW/i5txvN5ZNFtojQ2GCpaDlFNULgCHyOIXBaXLQZgdxRXCb7yWSnbYKShWMszBey5VXxwarg63xlo9f+K9GvMRSklSKZqCYZrQ1PEo3xo616gu3iSu3hGUpN3YVi+4d5DxVTLAYWvNoSg6iRYtRde/rMw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724685938; c=relaxed/simple; bh=JAzFcT8pBUv5FDzzhZgD0LlS/oqOvRD410hvJXG7SG8=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=GSytWJV3A8MsOd/nNiRvbvlXvDK7ZGerjdbypniMnUkr3pPos/0kN79rJ6JmovR7fpqhcCmsXOa4RPp61/jrL2GHbMjxTArX32ROzcpdgRPZcubz5flvSJoTIXoLOxbydsZjJMIbLuX/ua6C8rsPoN3ubxGpgvILNLmiqKTKAyk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=U3t4b3Od; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LbhSekJ2; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="U3t4b3Od"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LbhSekJ2" From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1724685928; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=HtqBVIjvewMJmwGbbGrtzP9wseneIF0JG8Xv5MYH9sg=; b=U3t4b3OdLu+GAFgNF+W13RPfUi9UpqJlkWXQo/rbtxrF5v3F/xRQunKmlWVgSEBMTg6p9H SnfM3j34lgAwsP+QxdwgsSCcglS3v9IpKrJ+A1OKiEqv2VnnbqvJ13QcQaMjWzLSnyLkPb 8YX+HBqyP/evDscLCNv1QU6RgC0lXWa9ptOHqu9VfLENdJWaHjvQKm9/FyAMM/FTEh4Jj3 2tmQsmzx0MyFVH3JkiSJxhhpuh/cynV1rX+yM8iV8fZ2hJAFIjVxwKgppVsfP9y06WdQYW VwSsRLNnEJPLAS0yNUrXAyAsezewrT8q5YP9MnQhb+9f9zA09h1hQd8jpE5nAA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1724685928; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=HtqBVIjvewMJmwGbbGrtzP9wseneIF0JG8Xv5MYH9sg=; b=LbhSekJ2kImTjTpI5qKezEgJdoF+OYa4K93qQL/ngQ9HbLWQbGvavIRCL9Qq9RBtd5Pbvi jsetTuVjOe5BLaAA== To: Sunil V L , "Rafael J . Wysocki" Cc: Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , Len Brown , Bjorn Helgaas , Anup Patel , Samuel Holland , Robert Moore , Conor Dooley , Haibo Xu , Andrew Jones , Atish Kumar Patra , Drew Fustini , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev Subject: Re: [PATCH v8 00/17] RISC-V: ACPI: Add external interrupt controller support In-Reply-To: References: <20240812005929.113499-1-sunilvl@ventanamicro.com> Date: Mon, 26 Aug 2024 17:25:28 +0200 Message-ID: <87mskzcnmf.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Mon, Aug 12 2024 at 06:37, Sunil V. L. wrote: > On Mon, Aug 12, 2024 at 06:29:12AM +0530, Sunil V L wrote: >> This series adds support for the below ECR approved by ASWG. >> 1) MADT - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing >> >> The series primarily enables irqchip drivers for RISC-V ACPI based >> platforms. > > This series has spent quite a bit of time now on the list. As you are > aware, few clarifications like _PIC codes are also done now. There is > no major change after you had agreed for the design. So, can this be > considered for the next release please? Rafael, if you want to take it through the ACPI tree, then for the irqchip parts please add: Acked-by: Thomas Gleixner Thanks, tglx