* [PATCH v2 1/2] Documentation: dt: dwc2: amend clocks property
2017-02-09 2:44 [PATCH v2 0/2] add multiple clock handling for dwc2 driver Frank Wang
@ 2017-02-09 2:44 ` Frank Wang
2017-02-09 2:44 ` [PATCH v2 2/2] usb: dwc2: add multiple clocks handling Frank Wang
1 sibling, 0 replies; 6+ messages in thread
From: Frank Wang @ 2017-02-09 2:44 UTC (permalink / raw)
To: johnyoun, gregkh, heiko
Cc: linux-kernel, linux-usb, linux-rockchip, huangtao, kever.yang,
william.wu, daniel.meng, frank.wang
Move 'clocks' to optional properties since not every platform
is going to need to specify it and add pmu/utmi/ulpi/utmifs
optional clocks into 'clock-names' list.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
Documentation/devicetree/bindings/usb/dwc2.txt | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 6c7c2bce..4d8b6dd 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -16,11 +16,18 @@ Required properties:
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
-- clocks: clock provider specifier
-- clock-names: shall be "otg"
-Refer to clk/clock-bindings.txt for generic clock consumer properties
Optional properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
+- clock-names: Contain the following optional clocks on demand:
+ - "otg": AHB clock. It is the scan clock for the core's AHB domain.
+ - "pmu": PMU hclk. Clock to PMU module when hibernation and/or ADP is enabled.
+ - "utmi": UTMI+ clock. Functionally used only when a UTMI PHY is selected,
+ but always used as the PHY domain clock during DFT Scan mode.
+ - "ulpi": ULPI PHY clock. Present only when a ULPI PHY is selected; negedge
+ is also used in DDR mode.
+ - "utmifs": UTMI FS clock. Present only when OTG_FSPHY_INTERFACE != 0.
+Refer to clk/clock-bindings.txt for generic clock consumer properties
- phys: phy provider specifier
- phy-names: shall be "usb2-phy"
Refer to phy/phy-bindings.txt for generic phy consumer properties
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] usb: dwc2: add multiple clocks handling
2017-02-09 2:44 [PATCH v2 0/2] add multiple clock handling for dwc2 driver Frank Wang
2017-02-09 2:44 ` [PATCH v2 1/2] Documentation: dt: dwc2: amend clocks property Frank Wang
@ 2017-02-09 2:44 ` Frank Wang
2017-02-09 12:31 ` Heiko Stübner
1 sibling, 1 reply; 6+ messages in thread
From: Frank Wang @ 2017-02-09 2:44 UTC (permalink / raw)
To: johnyoun, gregkh, heiko
Cc: linux-kernel, linux-usb, linux-rockchip, huangtao, kever.yang,
william.wu, daniel.meng, frank.wang
Since dwc2 may have one or more input clocks need to manage for some
platform, so this adds change clk to clk's array of struct dwc2_hsotg
to handle more clocks operation.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
drivers/usb/dwc2/core.h | 5 ++++-
drivers/usb/dwc2/platform.c | 39 ++++++++++++++++++++++++++-------------
2 files changed, 30 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 1a7e830..afde8a1 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -121,6 +121,9 @@ static inline void dwc2_writel(u32 value, void __iomem *addr)
/* Maximum number of Endpoints/HostChannels */
#define MAX_EPS_CHANNELS 16
+/* Maximum number of dwc2 input clocks */
+#define DWC2_MAX_CLKS 5
+
/* dwc2-hsotg declarations */
static const char * const dwc2_hsotg_supply_names[] = {
"vusb_d", /* digital USB supply, 1.2V */
@@ -913,7 +916,7 @@ struct dwc2_hsotg {
spinlock_t lock;
void *priv;
int irq;
- struct clk *clk;
+ struct clk *clks[DWC2_MAX_CLKS];
struct reset_control *reset;
unsigned int queuing_high_bandwidth:1;
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9564bc7..795fc43b 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -123,17 +123,20 @@ static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
{
struct platform_device *pdev = to_platform_device(hsotg->dev);
- int ret;
+ int clk, ret;
ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
hsotg->supplies);
if (ret)
return ret;
- if (hsotg->clk) {
- ret = clk_prepare_enable(hsotg->clk);
- if (ret)
+ for (clk = 0; clk < DWC2_MAX_CLKS && hsotg->clks[clk]; clk++) {
+ ret = clk_prepare_enable(hsotg->clks[clk]);
+ if (ret) {
+ while (--clk >= 0)
+ clk_disable_unprepare(hsotg->clks[clk]);
return ret;
+ }
}
if (hsotg->uphy) {
@@ -168,7 +171,7 @@ int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
{
struct platform_device *pdev = to_platform_device(hsotg->dev);
- int ret = 0;
+ int clk, ret = 0;
if (hsotg->uphy) {
usb_phy_shutdown(hsotg->uphy);
@@ -182,8 +185,9 @@ static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
if (ret)
return ret;
- if (hsotg->clk)
- clk_disable_unprepare(hsotg->clk);
+ for (clk = DWC2_MAX_CLKS - 1; clk >= 0; clk--)
+ if (hsotg->clks[clk])
+ clk_disable_unprepare(hsotg->clks[clk]);
ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
hsotg->supplies);
@@ -209,7 +213,7 @@ int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
{
- int i, ret;
+ int i, clk, ret;
hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
if (IS_ERR(hsotg->reset)) {
@@ -282,11 +286,20 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
hsotg->phyif = GUSBCFG_PHYIF8;
}
- /* Clock */
- hsotg->clk = devm_clk_get(hsotg->dev, "otg");
- if (IS_ERR(hsotg->clk)) {
- hsotg->clk = NULL;
- dev_dbg(hsotg->dev, "cannot get otg clock\n");
+ /* Clocks */
+ for (clk = 0; clk < DWC2_MAX_CLKS; clk++) {
+ hsotg->clks[clk] = of_clk_get(hsotg->dev->of_node, clk);
+ if (IS_ERR(hsotg->clks[clk])) {
+ ret = PTR_ERR(hsotg->clks[clk]);
+ if (ret == -EPROBE_DEFER) {
+ while (--clk >= 0)
+ clk_put(hsotg->clks[clk]);
+ return ret;
+ }
+
+ hsotg->clks[clk] = NULL;
+ break;
+ }
}
/* Regulators */
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread