From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCF9924336D for ; Sat, 11 Jul 2026 07:02:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783753348; cv=none; b=Z2MxvpeztoWWJzzYFCUcmql02dpvzOr9QXmQAVO0qA7ar6tGIedfZ5ZIszpYp4juKvBDjinCvPeqQ0vkpJ4dt2prm4tnA32p7Ams7WuQmyPLl7XHe/QXazspa9vi6q+A6Uil9LriTEt6gBC6t5AUnIoEwLPy/zE+xojJjMBEwDw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783753348; c=relaxed/simple; bh=Mm3TZrFIM4k6ZAM1dKQ9va8W0Hi6juUmAo8Da7e0XB4=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=jHd5GkEAkwSSl6YYQFYdRqQjMMTGQxSIGDdMGgAM4lOAOuCVhpuYnrmsNfdsiw9ErYiNmMDtYTwBxxZf1y767kov+/53BVJUpHa0SJ0yLxVkYeZuKTVvk5H/w5fnVhiQUsFeO9BNTt0yUsddwtVMGI/CmfiudgQ1OEEr1Nuwirk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MBZdrBQx; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MBZdrBQx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 690E61F000E9; Sat, 11 Jul 2026 07:02:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783753347; bh=iPBsIWUrBsXoeW5eL/O8oEjBIBAd/ymV6y7JDZrOoQQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=MBZdrBQxrWyMPgi6gK1WOaCBxfmz/FFO1SErr77QES9vSCeWDDodkOX9T2KsA8GOV LKHDnxcK8eGvsFczjG4e5x4x1arlh0TiXTt8DvY5SYJxtpGBo3cee+R9RZD7nQdZWj MMQ1PJw8O+QBqvzLnuQJhSooPjVixcjwfH3+ji/HLTI+6ERodANOvgUp0e4E5KKUT2 S8NrufZ3wt6k7/IqolAAELyOf8l9Ml1n6/5EtxbknkXJZZ7zZJ+RnBWluRFdujuqXj LtIJt6A8luQzBCj0t2Ob0eKvYoCx5WvgSzzJNO3Rr7SSjGh3Ly9onRfLDrTu+4BShp LMEqAvSL48wCg== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wiRjF-00000003wlm-0HsE; Sat, 11 Jul 2026 07:02:25 +0000 Date: Sat, 11 Jul 2026 08:04:13 +0100 Message-ID: <87o6ge57o2.wl-maz@kernel.org> From: Marc Zyngier To: Jinqian Yang Cc: , , , , , , , Subject: Re: [RFC PATCH v2] irqchip/gic-v3-its: enable dynamic MSI-X allocation In-Reply-To: <20260711022015.3049867-1-yangjinqian1@huawei.com> References: <20260711022015.3049867-1-yangjinqian1@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: yangjinqian1@huawei.com, lpieralisi@kernel.org, tglx@kernel.org, alex@shazbot.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, liuyonglong@huawei.com, wangzhou1@hisilicon.com, linuxarm@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sat, 11 Jul 2026 03:20:15 +0100, Jinqian Yang wrote: > > On ARM64 platforms with GICv3 ITS, VFIO PCI passthrough currently > cannot dynamically allocate MSI-X vectors after MSI-X has been > enabled. When QEMU needs to extend the vector range, it must > disable MSI-X, free all interrupts, then re-enable with a larger > allocation. This creates an interrupt loss window for already-active > vectors. > > Consider HNS3 with RoCE: NIC and RDMA share one PCI device and > ITS DeviceID, with MSI-X vectors partitioned as NIC (lower range) > then RoCE (starting at base_vector = num_nic_msi). In VFIO > passthrough, loading hns_roce after hns3 forces QEMU to tear down > all interrupts before re-allocating the larger range. During this > process, NIC interrupts may be lost. Testing confirmed that this > occasionally occurs, causing the network port reset to fail. This > appears to be unavoidable, as it's a standard approach adopted by > all network card vendors. > > On Hisilicon HIP09 (ARM64, GICv3/GICv4.1) with latest upstream kernel > and QEMU 8.2. VFIO passthrough of HNS3 NIC to VM: load both hns3 and > hns_roce_hw_v2 drivers and trigger FLR, this bug will occur occasionally. > After enabling dynamic MSIX allocation, this bug no longer occurs. > > Signed-off-by: Jinqian Yang > --- > Changes in v2: > - Updated the commit message to add test information. > > v1: https://lore.kernel.org/linux-arm-kernel/20260624025345.458387-1-yangjinqian1@huawei.com/ > --- > drivers/irqchip/irq-gic-its-msi-parent.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Marc Zyngier M. -- Jazz isn't dead. It just smells funny.