* [PATCH v2 01/10] MIPS: Export higher/highest relocation functions in uasm
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
@ 2023-10-27 22:10 ` Jiaxun Yang
2023-10-27 22:10 ` [PATCH v2 02/10] MIPS: spaces: Define a couple of handy macros Jiaxun Yang
` (9 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:10 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
Export uasm_rel_{higher,highest} functions.
Those functions can be helpful in dealing with 64bit immediates.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/uasm.h | 2 ++
arch/mips/mm/uasm.c | 6 ++++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 296bcf31abb5..12db6d2fca07 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -196,6 +196,8 @@ void uasm_build_label(struct uasm_label **lab, u32 *addr,
#ifdef CONFIG_64BIT
int uasm_in_compat_space_p(long addr);
#endif
+int uasm_rel_highest(long val);
+int uasm_rel_higher(long val);
int uasm_rel_hi(long val);
int uasm_rel_lo(long val);
void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 125140979d62..6846bf2084c5 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -425,7 +425,7 @@ int uasm_in_compat_space_p(long addr)
}
UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
-static int uasm_rel_highest(long val)
+int uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
@@ -433,8 +433,9 @@ static int uasm_rel_highest(long val)
return 0;
#endif
}
+UASM_EXPORT_SYMBOL(uasm_rel_highest);
-static int uasm_rel_higher(long val)
+int uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
@@ -442,6 +443,7 @@ static int uasm_rel_higher(long val)
return 0;
#endif
}
+UASM_EXPORT_SYMBOL(uasm_rel_higher);
int uasm_rel_hi(long val)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 02/10] MIPS: spaces: Define a couple of handy macros
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
2023-10-27 22:10 ` [PATCH v2 01/10] MIPS: Export higher/highest relocation functions in uasm Jiaxun Yang
@ 2023-10-27 22:10 ` Jiaxun Yang
2023-12-21 15:42 ` Thomas Bogendoerfer
2023-10-27 22:10 ` [PATCH v2 03/10] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Jiaxun Yang
` (8 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:10 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
KSEGX_SIZE is defined to size of each KSEG segment.
TO_CAC and TO_UNCAC are brought to 32bit builds as well,
TO_PHYS remains to be 64bit only as we want people to
use __pa to avoid mixup compat address space.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/addrspace.h | 5 +++++
arch/mips/include/asm/mach-generic/spaces.h | 5 +++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 59a48c60a065..03a5e2c8b5dc 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -47,6 +47,11 @@
*/
#define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000))
+/*
+ * Gives the size of each kernel segment
+ */
+#define KSEGX_SIZE 0x20000000
+
/*
* Returns the physical address of a CKSEGx / XKPHYS address
*/
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index b247575c5e69..05db19521e81 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -79,11 +79,12 @@
#endif
#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
-#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
#endif /* CONFIG_64BIT */
+#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
/*
* This handles the memory map.
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 02/10] MIPS: spaces: Define a couple of handy macros
2023-10-27 22:10 ` [PATCH v2 02/10] MIPS: spaces: Define a couple of handy macros Jiaxun Yang
@ 2023-12-21 15:42 ` Thomas Bogendoerfer
0 siblings, 0 replies; 20+ messages in thread
From: Thomas Bogendoerfer @ 2023-12-21 15:42 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, linux-kernel, gregory.clement, vladimir.kondratiev
On Fri, Oct 27, 2023 at 11:10:58PM +0100, Jiaxun Yang wrote:
> KSEGX_SIZE is defined to size of each KSEG segment.
>
> TO_CAC and TO_UNCAC are brought to 32bit builds as well,
> TO_PHYS remains to be 64bit only as we want people to
> use __pa to avoid mixup compat address space.
the problem here is, that in the 64bit case the macros work on every address
while in 32bit only the first 512MB address space is covered. So there
is a reason to not expose TO_CAC/TO_UNCAC for 32bit.
Which leaves the problem how to handle all the CKSEG[01]ADDR()
cases nicer for 64bit... I'd prefer an extra macro/inline function
which handles 32bit and 64bit accordingly. Not sure about the name
for it, but maybe something like
CKSEG[01]ADDR_OR_64BIT()
That would at least make clear (to me) this thing is special and might
return a XPHYS uncached address.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 03/10] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
2023-10-27 22:10 ` [PATCH v2 01/10] MIPS: Export higher/highest relocation functions in uasm Jiaxun Yang
2023-10-27 22:10 ` [PATCH v2 02/10] MIPS: spaces: Define a couple of handy macros Jiaxun Yang
@ 2023-10-27 22:10 ` Jiaxun Yang
2023-10-27 22:11 ` [PATCH v2 04/10] MIPS: Fix set_uncached_handler for ebase " Jiaxun Yang
` (7 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:10 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
Use {highest, higher, hi, lo} immediate loading sequence
to load 64 bit jump address for handler when kernel is
loaded to XKPHYS.
Co-developed-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Co-developed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/genex.S | 19 +++++++++++++++----
arch/mips/kernel/traps.c | 34 ++++++++++++++++++++++++----------
2 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index b6de8e88c1bd..fd765ad9ecac 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -272,11 +272,22 @@ NESTED(except_vec_vi, 0, sp)
.set push
.set noreorder
PTR_LA v1, except_vec_vi_handler
-FEXPORT(except_vec_vi_lui)
- lui v0, 0 /* Patched */
+#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
+FEXPORT(except_vec_vi_hi)
+ lui v0, 0 /* Patched */
+#else
+FEXPORT(except_vec_vi_highest)
+ lui v0, 0 /* Patched */
+FEXPORT(except_vec_vi_higher)
+ daddiu v0, 0 /* Patched */
+ dsll v0, 16
+FEXPORT(except_vec_vi_hi)
+ daddiu v0, 0 /* Patched */
+ dsll v0, 16
+#endif
jr v1
-FEXPORT(except_vec_vi_ori)
- ori v0, 0 /* Patched */
+FEXPORT(except_vec_vi_lo)
+ PTR_ADDIU v0, 0 /* Patched */
.set pop
END(except_vec_vi)
EXPORT(except_vec_vi_end)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 246c6a6b0261..60c513c51684 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2091,18 +2091,26 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
* If no shadow set is selected then use the default handler
* that does normal register saving and standard interrupt exit
*/
- extern const u8 except_vec_vi[], except_vec_vi_lui[];
- extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
+ extern const u8 except_vec_vi[], except_vec_vi_hi[];
+ extern const u8 except_vec_vi_lo[], except_vec_vi_end[];
+#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32)
+ extern const u8 except_vec_vi_highest[], except_vec_vi_higher[];
+#endif
extern const u8 rollback_except_vec_vi[];
const u8 *vec_start = using_rollback_handler() ?
rollback_except_vec_vi : except_vec_vi;
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
- const int lui_offset = except_vec_vi_lui - vec_start + 2;
- const int ori_offset = except_vec_vi_ori - vec_start + 2;
+ const int imm_offset = 2;
#else
- const int lui_offset = except_vec_vi_lui - vec_start;
- const int ori_offset = except_vec_vi_ori - vec_start;
+ const int imm_offset = 0;
+#endif
+#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32)
+ const int highest_offset = except_vec_vi_highest - vec_start + imm_offset;
+ const int higher_offset = except_vec_vi_higher - vec_start + imm_offset;
#endif
+ const int hi_offset = except_vec_vi_hi - vec_start + imm_offset;
+ const int lo_offset = except_vec_vi_lo - vec_start + imm_offset;
+
const int handler_len = except_vec_vi_end - vec_start;
if (handler_len > VECTORSPACING) {
@@ -2119,10 +2127,16 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
#else
handler_len);
#endif
- h = (u16 *)(b + lui_offset);
- *h = (handler >> 16) & 0xffff;
- h = (u16 *)(b + ori_offset);
- *h = (handler & 0xffff);
+#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32)
+ h = (u16 *)(b + highest_offset);
+ *h = uasm_rel_highest(handler);
+ h = (u16 *)(b + higher_offset);
+ *h = uasm_rel_higher(handler);
+#endif
+ h = (u16 *)(b + hi_offset);
+ *h = uasm_rel_hi(handler);
+ h = (u16 *)(b + lo_offset);
+ *h = uasm_rel_lo(handler);
local_flush_icache_range((unsigned long)b,
(unsigned long)(b+handler_len));
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 04/10] MIPS: Fix set_uncached_handler for ebase in XKPHYS
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
` (2 preceding siblings ...)
2023-10-27 22:10 ` [PATCH v2 03/10] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Jiaxun Yang
@ 2023-10-27 22:11 ` Jiaxun Yang
2023-10-27 22:11 ` [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation Jiaxun Yang
` (6 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:11 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
ebase may be in XKPHYS if memblock unable to allocate memory
within KSEG0 physical range.
To map ebase into uncached space we just convert it back to
physical address and then use platform's TO_UNCAC helper
to create mapping.
Co-developed-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Co-developed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/traps.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 60c513c51684..230728d76d11 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2346,7 +2346,7 @@ static const char panic_null_cerr[] =
void set_uncached_handler(unsigned long offset, void *addr,
unsigned long size)
{
- unsigned long uncached_ebase = CKSEG1ADDR(ebase);
+ unsigned long uncached_ebase = TO_UNCAC(__pa(ebase));
if (!addr)
panic(panic_null_cerr);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
` (3 preceding siblings ...)
2023-10-27 22:11 ` [PATCH v2 04/10] MIPS: Fix set_uncached_handler for ebase " Jiaxun Yang
@ 2023-10-27 22:11 ` Jiaxun Yang
2023-10-28 7:22 ` kernel test robot
` (2 more replies)
2023-10-27 22:11 ` [PATCH v2 06/10] MIPS: Allow kernel base to be set from Kconfig for all platforms Jiaxun Yang
` (5 subsequent siblings)
10 siblings, 3 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:11 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
Now the exception vector for CPS systems are allocated on-fly
with memblock as well.
It will try to allocate from KSEG1 first, and then try to allocate
in low 4G if possible.
The main reset vector is now generated by uasm, to avoid tons
of patches to the code. Other vectors are copied to the location
later.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/mips-cm.h | 1 +
arch/mips/include/asm/smp-cps.h | 4 +-
arch/mips/kernel/cps-vec.S | 110 ++++++++-------------
arch/mips/kernel/smp-cps.c | 167 +++++++++++++++++++++++++++-----
arch/mips/kernel/traps.c | 2 +
5 files changed, 186 insertions(+), 98 deletions(-)
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 23c67c0871b1..15d8d69de455 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other)
/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
+#define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
/* GCR_Cx_ID - Identify the current core */
GCR_CX_ACCESSOR_RO(32, 0x028, id)
diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h
index 22a572b70fe3..39a602e5fecc 100644
--- a/arch/mips/include/asm/smp-cps.h
+++ b/arch/mips/include/asm/smp-cps.h
@@ -24,7 +24,7 @@ struct core_boot_config {
extern struct core_boot_config *mips_cps_core_bootcfg;
-extern void mips_cps_core_entry(void);
+extern void mips_cps_core_boot(int cca, void __iomem *gcr_base);
extern void mips_cps_core_init(void);
extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
@@ -32,8 +32,6 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
extern void mips_cps_pm_save(void);
extern void mips_cps_pm_restore(void);
-extern void *mips_cps_core_entry_patch_end;
-
#ifdef CONFIG_MIPS_CPS
extern bool mips_cps_smp_in_use(void);
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 64ecfdac6580..8870a2dbc35a 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -4,6 +4,8 @@
* Author: Paul Burton <paul.burton@mips.com>
*/
+#include <linux/init.h>
+
#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
@@ -81,40 +83,48 @@
nop
.endm
+ __INIT
+LEAF(excep_tlbfill)
+ DUMP_EXCEP("TLB Fill")
+ b .
+ nop
+ END(excep_tlbfill)
-.balign 0x1000
+LEAF(excep_xtlbfill)
+ DUMP_EXCEP("XTLB Fill")
+ b .
+ nop
+ END(excep_xtlbfill)
-LEAF(mips_cps_core_entry)
- /*
- * These first several instructions will be patched by cps_smp_setup to load the
- * CCA to use into register s0 and GCR base address to register s1.
- */
- .rept CPS_ENTRY_PATCH_INSNS
- nop
- .endr
+LEAF(excep_cache)
+ DUMP_EXCEP("Cache")
+ b .
+ nop
+ END(excep_cache)
- .global mips_cps_core_entry_patch_end
-mips_cps_core_entry_patch_end:
+LEAF(excep_genex)
+ DUMP_EXCEP("General")
+ b .
+ nop
+ END(excep_genex)
- /* Check whether we're here due to an NMI */
- mfc0 k0, CP0_STATUS
- and k0, k0, ST0_NMI
- beqz k0, not_nmi
+LEAF(excep_intex)
+ DUMP_EXCEP("Interrupt")
+ b .
nop
+ END(excep_intex)
- /* This is an NMI */
- PTR_LA k0, nmi_handler
+LEAF(excep_ejtag)
+ PTR_LA k0, ejtag_debug_handler
jr k0
nop
+ END(excep_ejtag)
+ __FINIT
-not_nmi:
- /* Setup Cause */
- li t0, CAUSEF_IV
- mtc0 t0, CP0_CAUSE
-
- /* Setup Status */
- li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
- mtc0 t0, CP0_STATUS
+LEAF(mips_cps_core_boot)
+ /* Save CCA and GCR base */
+ move s0, a0
+ move s1, a1
/* We don't know how to do coherence setup on earlier ISA */
#if MIPS_ISA_REV > 0
@@ -178,49 +188,7 @@ not_nmi:
PTR_L sp, VPEBOOTCFG_SP(v1)
jr t1
nop
- END(mips_cps_core_entry)
-
-.org 0x200
-LEAF(excep_tlbfill)
- DUMP_EXCEP("TLB Fill")
- b .
- nop
- END(excep_tlbfill)
-
-.org 0x280
-LEAF(excep_xtlbfill)
- DUMP_EXCEP("XTLB Fill")
- b .
- nop
- END(excep_xtlbfill)
-
-.org 0x300
-LEAF(excep_cache)
- DUMP_EXCEP("Cache")
- b .
- nop
- END(excep_cache)
-
-.org 0x380
-LEAF(excep_genex)
- DUMP_EXCEP("General")
- b .
- nop
- END(excep_genex)
-
-.org 0x400
-LEAF(excep_intex)
- DUMP_EXCEP("Interrupt")
- b .
- nop
- END(excep_intex)
-
-.org 0x480
-LEAF(excep_ejtag)
- PTR_LA k0, ejtag_debug_handler
- jr k0
- nop
- END(excep_ejtag)
+ END(mips_cps_core_boot)
LEAF(mips_cps_core_init)
#ifdef CONFIG_MIPS_MT_SMP
@@ -428,7 +396,7 @@ LEAF(mips_cps_boot_vpes)
/* Calculate a pointer to the VPEs struct vpe_boot_config */
li t0, VPEBOOTCFG_SIZE
mul t0, t0, ta1
- addu t0, t0, ta3
+ PTR_ADDU t0, t0, ta3
/* Set the TC restart PC */
lw t1, VPEBOOTCFG_PC(t0)
@@ -603,10 +571,10 @@ dcache_done:
lw $1, TI_CPU(gp)
sll $1, $1, LONGLOG
PTR_LA \dest, __per_cpu_offset
- addu $1, $1, \dest
+ PTR_ADDU $1, $1, \dest
lw $1, 0($1)
PTR_LA \dest, cps_cpu_state
- addu \dest, \dest, $1
+ PTR_ADDU \dest, \dest, $1
.set pop
.endm
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index dd55d59b88db..9aad678a32bd 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -7,6 +7,7 @@
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/memblock.h>
#include <linux/sched/task_stack.h>
#include <linux/sched/hotplug.h>
#include <linux/slab.h>
@@ -25,7 +26,33 @@
#include <asm/time.h>
#include <asm/uasm.h>
+#define BEV_VEC_SIZE 0x500
+#define BEV_VEC_ALIGN 0x1000
+
+#define A0 4
+#define A1 5
+#define T9 25
+#define K0 26
+#define K1 27
+
+#define C0_STATUS 12, 0
+#define C0_CAUSE 13, 0
+
+#define ST0_NMI_BIT 19
+#ifdef CONFIG_64BIT
+#define ST0_KX_IF_64 ST0_KX
+#else
+#define ST0_KX_IF_64 0
+#endif
+
+enum label_id {
+ label_not_nmi = 1,
+};
+
+UASM_L_LA(_not_nmi)
+
static DECLARE_BITMAP(core_power, NR_CPUS);
+static uint32_t core_entry_reg;
struct core_boot_config *mips_cps_core_bootcfg;
@@ -34,10 +61,113 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
return min(smp_max_threads, mips_cps_numvps(cluster, core));
}
+static void __init *mips_cps_build_core_entry(void *addr)
+{
+ extern void (*nmi_handler)(void);
+ u32 *p = addr;
+ u32 val;
+ struct uasm_label labels[2];
+ struct uasm_reloc relocs[2];
+ struct uasm_label *l = labels;
+ struct uasm_reloc *r = relocs;
+
+ memset(labels, 0, sizeof(labels));
+ memset(relocs, 0, sizeof(relocs));
+
+ uasm_i_mfc0(&p, K0, C0_STATUS);
+ if (cpu_has_mips_r2_r6)
+ uasm_i_ext(&p, K0, K0, ST0_NMI_BIT, 1);
+ else {
+ uasm_i_srl(&p, K0, K0, ST0_NMI_BIT);
+ uasm_i_andi(&p, K0, K0, 0x1);
+ }
+
+ uasm_il_bnez(&p, &r, K0, label_not_nmi);
+ uasm_i_nop(&p);
+ UASM_i_LA(&p, K0, (long)&nmi_handler);
+
+ uasm_l_not_nmi(&l, p);
+
+ val = CAUSEF_IV;
+ uasm_i_lui(&p, K0, val >> 16);
+ uasm_i_ori(&p, K0, K0, val & 0xffff);
+ uasm_i_mtc0(&p, K0, C0_CAUSE);
+ val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64;
+ uasm_i_lui(&p, K0, val >> 16);
+ uasm_i_ori(&p, K0, K0, val & 0xffff);
+ uasm_i_mtc0(&p, K0, C0_STATUS);
+ uasm_i_ehb(&p);
+ uasm_i_ori(&p, A0, 0, read_c0_config() & CONF_CM_CMASK);
+ UASM_i_LA(&p, A1, (long)mips_gcr_base);
+#if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT)
+ UASM_i_LA(&p, T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot)));
+#else
+ UASM_i_LA(&p, T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot)));
+#endif
+ uasm_i_jr(&p, T9);
+ uasm_i_nop(&p);
+
+ uasm_resolve_relocs(relocs, labels);
+
+ return p;
+}
+
+static int __init setup_cps_vecs(void)
+{
+ extern void excep_tlbfill(void);
+ extern void excep_xtlbfill(void);
+ extern void excep_cache(void);
+ extern void excep_genex(void);
+ extern void excep_intex(void);
+ extern void excep_ejtag(void);
+ phys_addr_t cps_vec_pa;
+ void *cps_vec;
+
+ /* Try to allocate in KSEG1 first */
+ cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
+ 0x0, KSEGX_SIZE - 1);
+
+ if (cps_vec_pa)
+ core_entry_reg = CKSEG1ADDR(cps_vec_pa) &
+ CM_GCR_Cx_RESET_BASE_BEVEXCBASE;
+
+ if (!cps_vec_pa && mips_cm_is64) {
+ cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
+ 0x0, SZ_4G - 1);
+ if (cps_vec_pa)
+ core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) |
+ CM_GCR_Cx_RESET_BASE_MODE;
+ }
+
+ if (!cps_vec_pa)
+ return -ENOMEM;
+
+ /* We want to ensure cache is clean before writing uncached mem */
+ blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE);
+ bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
+ __sync();
+
+ cps_vec = (void *)TO_UNCAC(cps_vec_pa);
+ mips_cps_build_core_entry(cps_vec);
+
+ memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80);
+ memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80);
+ memcpy(cps_vec + 0x300, &excep_cache, 0x80);
+ memcpy(cps_vec + 0x380, &excep_genex, 0x80);
+ memcpy(cps_vec + 0x400, &excep_intex, 0x80);
+ memcpy(cps_vec + 0x480, &excep_ejtag, 0x80);
+
+ /* Make sure no prefetched data in cache */
+ blast_inv_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE);
+ bc_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
+ __sync();
+
+ return 0;
+}
+
static void __init cps_smp_setup(void)
{
unsigned int nclusters, ncores, nvpes, core_vpes;
- unsigned long core_entry;
int cl, c, v;
/* Detect & record VPE topology */
@@ -94,10 +224,11 @@ static void __init cps_smp_setup(void)
/* Make core 0 coherent with everything */
write_gcr_cl_coherence(0xff);
- if (mips_cm_revision() >= CM_REV_CM3) {
- core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
- write_gcr_bev_base(core_entry);
- }
+ if (setup_cps_vecs())
+ pr_err("Failed to setup CPS vectors\n");
+
+ if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3)
+ write_gcr_bev_base(core_entry_reg);
#ifdef CONFIG_MIPS_MT_FPAFF
/* If we have an FPU, enroll ourselves in the FPU-full mask */
@@ -110,10 +241,14 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
{
unsigned ncores, core_vpes, c, cca;
bool cca_unsuitable, cores_limited;
- u32 *entry_code;
mips_mt_set_cpuoptions();
+ if (!core_entry_reg) {
+ pr_err("core_entry address unsuitable, disabling smp-cps\n");
+ goto err_out;
+ }
+
/* Detect whether the CCA is unsuited to multi-core SMP */
cca = read_c0_config() & CONF_CM_CMASK;
switch (cca) {
@@ -145,20 +280,6 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
(cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
cpu_has_dc_aliases ? "dcache aliasing" : "");
- /*
- * Patch the start of mips_cps_core_entry to provide:
- *
- * s0 = kseg0 CCA
- */
- entry_code = (u32 *)&mips_cps_core_entry;
- uasm_i_addiu(&entry_code, 16, 0, cca);
- UASM_i_LA(&entry_code, 17, (long)mips_gcr_base);
- BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end);
- blast_dcache_range((unsigned long)&mips_cps_core_entry,
- (unsigned long)entry_code);
- bc_wback_inv((unsigned long)&mips_cps_core_entry,
- (void *)entry_code - (void *)&mips_cps_core_entry);
- __sync();
/* Allocate core boot configuration structs */
ncores = mips_cps_numcores(0);
@@ -213,7 +334,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
/* Set its reset vector */
- write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
+ write_gcr_co_reset_base(core_entry_reg);
/* Ensure its coherency is disabled */
write_gcr_co_coherence(0);
@@ -290,7 +411,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
- unsigned long core_entry;
unsigned int remote;
int err;
@@ -314,8 +434,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
if (cpu_has_vp) {
mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
- core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
- write_gcr_co_reset_base(core_entry);
+ write_gcr_co_reset_base(core_entry_reg);
mips_cm_unlock_other();
}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 230728d76d11..ea59d321f713 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -74,6 +74,8 @@
#include "access-helper.h"
+#define MAX(a, b) ((a) >= (b) ? (a) : (b))
+
extern void check_wait(void);
extern asmlinkage void rollback_handle_int(void);
extern asmlinkage void handle_int(void);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation
2023-10-27 22:11 ` [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation Jiaxun Yang
@ 2023-10-28 7:22 ` kernel test robot
2023-11-08 16:30 ` Gregory CLEMENT
2023-12-22 12:18 ` Thomas Bogendoerfer
2 siblings, 0 replies; 20+ messages in thread
From: kernel test robot @ 2023-10-28 7:22 UTC (permalink / raw)
To: Jiaxun Yang, linux-mips
Cc: oe-kbuild-all, linux-kernel, tsbogend, gregory.clement,
vladimir.kondratiev, Jiaxun Yang
Hi Jiaxun,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.6-rc7 next-20231027]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jiaxun-Yang/MIPS-Export-higher-highest-relocation-functions-in-uasm/20231028-061419
base: linus/master
patch link: https://lore.kernel.org/r/20231027221106.405666-6-jiaxun.yang%40flygoat.com
patch subject: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation
config: mips-allyesconfig (https://download.01.org/0day-ci/archive/20231028/202310281539.nqlVBqte-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231028/202310281539.nqlVBqte-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310281539.nqlVBqte-lkp@intel.com/
All warnings (new ones prefixed by >>):
arch/mips/kernel/smp-cps.c: In function 'setup_cps_vecs':
>> arch/mips/kernel/smp-cps.c:150:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
150 | cps_vec = (void *)TO_UNCAC(cps_vec_pa);
| ^
vim +150 arch/mips/kernel/smp-cps.c
114
115 static int __init setup_cps_vecs(void)
116 {
117 extern void excep_tlbfill(void);
118 extern void excep_xtlbfill(void);
119 extern void excep_cache(void);
120 extern void excep_genex(void);
121 extern void excep_intex(void);
122 extern void excep_ejtag(void);
123 phys_addr_t cps_vec_pa;
124 void *cps_vec;
125
126 /* Try to allocate in KSEG1 first */
127 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
128 0x0, KSEGX_SIZE - 1);
129
130 if (cps_vec_pa)
131 core_entry_reg = CKSEG1ADDR(cps_vec_pa) &
132 CM_GCR_Cx_RESET_BASE_BEVEXCBASE;
133
134 if (!cps_vec_pa && mips_cm_is64) {
135 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
136 0x0, SZ_4G - 1);
137 if (cps_vec_pa)
138 core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) |
139 CM_GCR_Cx_RESET_BASE_MODE;
140 }
141
142 if (!cps_vec_pa)
143 return -ENOMEM;
144
145 /* We want to ensure cache is clean before writing uncached mem */
146 blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE);
147 bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
148 __sync();
149
> 150 cps_vec = (void *)TO_UNCAC(cps_vec_pa);
151 mips_cps_build_core_entry(cps_vec);
152
153 memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80);
154 memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80);
155 memcpy(cps_vec + 0x300, &excep_cache, 0x80);
156 memcpy(cps_vec + 0x380, &excep_genex, 0x80);
157 memcpy(cps_vec + 0x400, &excep_intex, 0x80);
158 memcpy(cps_vec + 0x480, &excep_ejtag, 0x80);
159
160 /* Make sure no prefetched data in cache */
161 blast_inv_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE);
162 bc_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
163 __sync();
164
165 return 0;
166 }
167
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation
2023-10-27 22:11 ` [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation Jiaxun Yang
2023-10-28 7:22 ` kernel test robot
@ 2023-11-08 16:30 ` Gregory CLEMENT
2023-11-09 13:12 ` Jiaxun Yang
2023-12-22 12:18 ` Thomas Bogendoerfer
2 siblings, 1 reply; 20+ messages in thread
From: Gregory CLEMENT @ 2023-11-08 16:30 UTC (permalink / raw)
To: Jiaxun Yang, linux-mips
Cc: linux-kernel, tsbogend, vladimir.kondratiev, Jiaxun Yang
Hello Jiaxun,
> Now the exception vector for CPS systems are allocated on-fly
> with memblock as well.
>
> It will try to allocate from KSEG1 first, and then try to allocate
> in low 4G if possible.
>
> The main reset vector is now generated by uasm, to avoid tons
> of patches to the code. Other vectors are copied to the location
> later.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> +
> +static int __init setup_cps_vecs(void)
> +{
[...]
> +
> + /* We want to ensure cache is clean before writing uncached mem */
> + blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) +
> BEV_VEC_SIZE);
In my case this call failed because when setup_cps_vecs is called, the
cache information are not initialized yet!
As a workaround I moved the cpu_cache_init() call before
plat_smp_setup() in the /arch/mips/kernel/setup.c file.
Obviously it is not the right thing to do, but it shows that the cache
related function are called too early. For example, in
blast_dcache_range, the value returned by cpu_dcache_line_size was 0
instead of 64, because the value cpu_data[0].dcache.linesz was not set
yet.
So I wonder who it managed to work in your setup. What is the machine
running in QEMU ?
Does it use someting like the following line ?
#define cpu_dcache_line_size() 32
> + bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
> + __sync();
> +
> + cps_vec = (void *)TO_UNCAC(cps_vec_pa);
> + mips_cps_build_core_entry(cps_vec);
> +
> + memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80);
> + memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80);
> + memcpy(cps_vec + 0x300, &excep_cache, 0x80);
> + memcpy(cps_vec + 0x380, &excep_genex, 0x80);
> + memcpy(cps_vec + 0x400, &excep_intex, 0x80);
> + memcpy(cps_vec + 0x480, &excep_ejtag, 0x80);
> +
> + /* Make sure no prefetched data in cache */
> + blast_inv_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE);
> + bc_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
> + __sync();
> +
> + return 0;
> +}
[...]
> /* If we have an FPU, enroll ourselves in the FPU-full mask */
> @@ -110,10 +241,14 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
> {
> unsigned ncores, core_vpes, c, cca;
> bool cca_unsuitable, cores_limited;
> - u32 *entry_code;
>
> mips_mt_set_cpuoptions();
>
> + if (!core_entry_reg) {
> + pr_err("core_entry address unsuitable, disabling smp-cps\n");
> + goto err_out;
> + }
> +
> /* Detect whether the CCA is unsuited to multi-core SMP */
> cca = read_c0_config() & CONF_CM_CMASK;
> switch (cca) {
> @@ -145,20 +280,6 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
> (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
> cpu_has_dc_aliases ? "dcache aliasing" : "");
>
> - /*
> - * Patch the start of mips_cps_core_entry to provide:
> - *
> - * s0 = kseg0 CCA
> - */
> - entry_code = (u32 *)&mips_cps_core_entry;
> - uasm_i_addiu(&entry_code, 16, 0, cca);
> - UASM_i_LA(&entry_code, 17, (long)mips_gcr_base);
> - BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end);
> - blast_dcache_range((unsigned long)&mips_cps_core_entry,
> - (unsigned long)entry_code);
> - bc_wback_inv((unsigned long)&mips_cps_core_entry,
> - (void *)entry_code - (void *)&mips_cps_core_entry);
> - __sync();
The original code here was called later during boot from
kernel_init_freeable() which is called by kernel_init() after all the
calls in start_kernel. That's why there were no issue before the move.
Gregory
>
> /* Allocate core boot configuration structs */
> ncores = mips_cps_numcores(0);
> @@ -213,7 +334,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
> mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
>
> /* Set its reset vector */
> - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
> + write_gcr_co_reset_base(core_entry_reg);
>
> /* Ensure its coherency is disabled */
> write_gcr_co_coherence(0);
> @@ -290,7 +411,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
> unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
> struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
> struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
> - unsigned long core_entry;
> unsigned int remote;
> int err;
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation
2023-11-08 16:30 ` Gregory CLEMENT
@ 2023-11-09 13:12 ` Jiaxun Yang
0 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-11-09 13:12 UTC (permalink / raw)
To: Gregory CLEMENT, linux-mips@vger.kernel.org
Cc: linux-kernel, Thomas Bogendoerfer, vladimir.kondratiev
在2023年11月8日十一月 下午4:30，Gregory CLEMENT写道：
> Hello Jiaxun,
>
>> Now the exception vector for CPS systems are allocated on-fly
>> with memblock as well.
>>
>> It will try to allocate from KSEG1 first, and then try to allocate
>> in low 4G if possible.
>>
>> The main reset vector is now generated by uasm, to avoid tons
>> of patches to the code. Other vectors are copied to the location
>> later.
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>
>> +
>> +static int __init setup_cps_vecs(void)
>> +{
> [...]
>> +
>> + /* We want to ensure cache is clean before writing uncached mem */
>> + blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) +
>> BEV_VEC_SIZE);
>
> In my case this call failed because when setup_cps_vecs is called, the
> cache information are not initialized yet!
>
> As a workaround I moved the cpu_cache_init() call before
> plat_smp_setup() in the /arch/mips/kernel/setup.c file.
>
> Obviously it is not the right thing to do, but it shows that the cache
> related function are called too early. For example, in
> blast_dcache_range, the value returned by cpu_dcache_line_size was 0
> instead of 64, because the value cpu_data[0].dcache.linesz was not set
> yet.
Oops, that's a problem!
>
> So I wonder who it managed to work in your setup. What is the machine
> running in QEMU .
I'm using QEMU boston with vmlinux only.
QEMU does not emulate Cache at all so that won't be a problem on QEMU
but it may be a problem for actual hardware.
The proper solution might be leave allocation here but move uasm generation
to a later point.
>
> Does it use someting like the following line ?
> #define cpu_dcache_line_size() 32
>
>
>> + bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
>> + __sync();
>> +
>> + cps_vec = (void *)TO_UNCAC(cps_vec_pa);
>> + mips_cps_build_core_entry(cps_vec);
>> +
>> + memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80);
>> + memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80);
>> + memcpy(cps_vec + 0x300, &excep_cache, 0x80);
>> + memcpy(cps_vec + 0x380, &excep_genex, 0x80);
>> + memcpy(cps_vec + 0x400, &excep_intex, 0x80);
>> + memcpy(cps_vec + 0x480, &excep_ejtag, 0x80);
>> +
>> + /* Make sure no prefetched data in cache */
>> + blast_inv_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE);
>> + bc_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
>> + __sync();
>> +
>> + return 0;
>> +}
>
> [...]
>
>> /* If we have an FPU, enroll ourselves in the FPU-full mask */
>> @@ -110,10 +241,14 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
>> {
>> unsigned ncores, core_vpes, c, cca;
>> bool cca_unsuitable, cores_limited;
>> - u32 *entry_code;
>>
>> mips_mt_set_cpuoptions();
>>
>> + if (!core_entry_reg) {
>> + pr_err("core_entry address unsuitable, disabling smp-cps\n");
>> + goto err_out;
>> + }
>> +
>> /* Detect whether the CCA is unsuited to multi-core SMP */
>> cca = read_c0_config() & CONF_CM_CMASK;
>> switch (cca) {
>> @@ -145,20 +280,6 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
>> (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
>> cpu_has_dc_aliases ? "dcache aliasing" : "");
>>
>> - /*
>> - * Patch the start of mips_cps_core_entry to provide:
>> - *
>> - * s0 = kseg0 CCA
>> - */
>> - entry_code = (u32 *)&mips_cps_core_entry;
>> - uasm_i_addiu(&entry_code, 16, 0, cca);
>> - UASM_i_LA(&entry_code, 17, (long)mips_gcr_base);
>> - BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end);
>> - blast_dcache_range((unsigned long)&mips_cps_core_entry,
>> - (unsigned long)entry_code);
>> - bc_wback_inv((unsigned long)&mips_cps_core_entry,
>> - (void *)entry_code - (void *)&mips_cps_core_entry);
>> - __sync();
>
> The original code here was called later during boot from
> kernel_init_freeable() which is called by kernel_init() after all the
> calls in start_kernel. That's why there were no issue before the move.
I guess move uasm generation code here will be helpful :-)
>
> Gregory
>
>>
--
- Jiaxun
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation
2023-10-27 22:11 ` [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation Jiaxun Yang
2023-10-28 7:22 ` kernel test robot
2023-11-08 16:30 ` Gregory CLEMENT
@ 2023-12-22 12:18 ` Thomas Bogendoerfer
2023-12-22 12:40 ` Jiaxun Yang
2 siblings, 1 reply; 20+ messages in thread
From: Thomas Bogendoerfer @ 2023-12-22 12:18 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, linux-kernel, gregory.clement, vladimir.kondratiev
On Fri, Oct 27, 2023 at 11:11:01PM +0100, Jiaxun Yang wrote:
> Now the exception vector for CPS systems are allocated on-fly
> with memblock as well.
>
> It will try to allocate from KSEG1 first, and then try to allocate
> in low 4G if possible.
>
> The main reset vector is now generated by uasm, to avoid tons
> of patches to the code. Other vectors are copied to the location
> later.
this patch does way to many things in one go. What is needed to
make a kernel working with an ebase anyware in XPHYS ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation
2023-12-22 12:18 ` Thomas Bogendoerfer
@ 2023-12-22 12:40 ` Jiaxun Yang
0 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-12-22 12:40 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, linux-kernel, gregory.clement, vladimir.kondratiev
在 2023/12/22 12:18, Thomas Bogendoerfer 写道:
> On Fri, Oct 27, 2023 at 11:11:01PM +0100, Jiaxun Yang wrote:
>> Now the exception vector for CPS systems are allocated on-fly
>> with memblock as well.
>>
>> It will try to allocate from KSEG1 first, and then try to allocate
>> in low 4G if possible.
>>
>> The main reset vector is now generated by uasm, to avoid tons
>> of patches to the code. Other vectors are copied to the location
>> later.
> this patch does way to many things in one go. What is needed to
> make a kernel working with an ebase anyware in XPHYS ?
As we have some silly restrictions on the placement of CPS reset_base, it's
impossible to put CPS's cluster reset base "anywhere".
You'll have to make entry code in cps-vec.S relocatable to allow it to
be moved
by kernel at run time. Either patching the code or generate by uasm.
Thanks
- Jiaxun
>
> Thomas.
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 06/10] MIPS: Allow kernel base to be set from Kconfig for all platforms
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
` (4 preceding siblings ...)
2023-10-27 22:11 ` [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation Jiaxun Yang
@ 2023-10-27 22:11 ` Jiaxun Yang
2023-10-27 22:11 ` [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint offset Jiaxun Yang
` (4 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:11 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
There are some platforms in wild that generic loading address won't
work with them due to memory layout.
Allow PHYSICAL_START to be override from Kconfig, introduce
PHYSICAL_START_BOOL symbol as powerpc did.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bc8421859006..bfedc8b48a81 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2884,12 +2884,22 @@ config ARCH_SUPPORTS_KEXEC
config ARCH_SUPPORTS_CRASH_DUMP
def_bool y
+config PHYSICAL_START_BOOL
+ bool "Set physical address where the kernel is loaded"
+ default y if CRASH_DUMP
+ help
+ This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel
+ is loaded.
+
+ Say N here unless you know what you are doing.
+
config PHYSICAL_START
- hex "Physical address where the kernel is loaded"
- default "0xffffffff84000000"
- depends on CRASH_DUMP
+ hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL
+ default "0xffffffff84000000" if CRASH_DUMP
+ default "0xffffffff80100000"
help
- This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
+ This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel
+ is loaded.
If you plan to use kernel for capturing the crash dump change
this value to start of the reserved region (the "X" value as
specified in the "crashkernel=YM@XM" command line boot parameter
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint offset
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
` (5 preceding siblings ...)
2023-10-27 22:11 ` [PATCH v2 06/10] MIPS: Allow kernel base to be set from Kconfig for all platforms Jiaxun Yang
@ 2023-10-27 22:11 ` Jiaxun Yang
2023-12-22 12:19 ` Thomas Bogendoerfer
2023-10-27 22:11 ` [PATCH v2 08/10] MIPS: Avoid unnecessary reservation of exception space Jiaxun Yang
` (3 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:11 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
Some BMIPS cpus has none standard start offset for vector interrupts.
Handle those CPUs in vector size calculation and handler setup process.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++---------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ea59d321f713..651c9ec6265a 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -74,7 +74,6 @@
#include "access-helper.h"
-#define MAX(a, b) ((a) >= (b) ? (a) : (b))
extern void check_wait(void);
extern asmlinkage void rollback_handle_int(void);
@@ -2005,6 +2004,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs)
unsigned long ebase;
EXPORT_SYMBOL_GPL(ebase);
unsigned long exception_handlers[32];
+static unsigned long vi_vecbase;
unsigned long vi_handlers[64];
void reserve_exception_space(phys_addr_t addr, unsigned long size)
@@ -2074,7 +2074,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
handler = (unsigned long) addr;
vi_handlers[n] = handler;
- b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
+ b = (unsigned char *)(vi_vecbase + n*VECTORSPACING);
if (srs >= srssets)
panic("Shadow register set %d not supported", srs);
@@ -2370,20 +2370,33 @@ void __init trap_init(void)
extern char except_vec3_generic;
extern char except_vec4;
extern char except_vec3_r4000;
- unsigned long i, vec_size;
+ unsigned long i, vec_size, vi_vec_offset;
phys_addr_t ebase_pa;
check_wait();
+ if (cpu_has_veic || cpu_has_vint) {
+ switch (current_cpu_type()) {
+ case CPU_BMIPS3300:
+ case CPU_BMIPS4380:
+ vi_vec_offset = 0x400;
+ break;
+ case CPU_BMIPS5000:
+ vi_vec_offset = 0x1000;
+ break;
+ default:
+ vi_vec_offset = 0x200;
+ break;
+ }
+ vec_size = vi_vec_offset + VECTORSPACING*64;
+ } else {
+ vec_size = 0x400;
+ }
+
if (!cpu_has_mips_r2_r6) {
ebase = CAC_BASE;
- vec_size = 0x400;
} else {
- if (cpu_has_veic || cpu_has_vint)
- vec_size = 0x200 + VECTORSPACING*64;
- else
- vec_size = PAGE_SIZE;
-
+ vec_size = max(vec_size, PAGE_SIZE);
ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
if (!ebase_pa)
panic("%s: Failed to allocate %lu bytes align=0x%x\n",
@@ -2450,6 +2463,7 @@ void __init trap_init(void)
* Initialise interrupt handlers
*/
if (cpu_has_veic || cpu_has_vint) {
+ vi_vecbase = ebase + vi_vec_offset;
int nvec = cpu_has_veic ? 64 : 8;
for (i = 0; i < nvec; i++)
set_vi_handler(i, NULL);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint offset
2023-10-27 22:11 ` [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint offset Jiaxun Yang
@ 2023-12-22 12:19 ` Thomas Bogendoerfer
2023-12-22 12:47 ` Jiaxun Yang
0 siblings, 1 reply; 20+ messages in thread
From: Thomas Bogendoerfer @ 2023-12-22 12:19 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, linux-kernel, gregory.clement, vladimir.kondratiev
On Fri, Oct 27, 2023 at 11:11:03PM +0100, Jiaxun Yang wrote:
> Some BMIPS cpus has none standard start offset for vector interrupts.
>
> Handle those CPUs in vector size calculation and handler setup process.
hmm, I see no connection to what this series is fixing. How does it
work without this patch ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint offset
2023-12-22 12:19 ` Thomas Bogendoerfer
@ 2023-12-22 12:47 ` Jiaxun Yang
0 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-12-22 12:47 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, linux-kernel, gregory.clement, vladimir.kondratiev
在 2023/12/22 12:19, Thomas Bogendoerfer 写道:
> On Fri, Oct 27, 2023 at 11:11:03PM +0100, Jiaxun Yang wrote:
>> Some BMIPS cpus has none standard start offset for vector interrupts.
>>
>> Handle those CPUs in vector size calculation and handler setup process.
> hmm, I see no connection to what this series is fixing. How does it
> work without this patch ?
In this series reservation of exception vector is moved to here, so it's
critical
to have correct size.
Thanks
- Jiaxun
>
> Thomas.
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 08/10] MIPS: Avoid unnecessary reservation of exception space
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
` (6 preceding siblings ...)
2023-10-27 22:11 ` [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint offset Jiaxun Yang
@ 2023-10-27 22:11 ` Jiaxun Yang
2023-10-27 22:11 ` [PATCH v2 09/10] MIPS: traps: Enhance memblock ebase allocation process Jiaxun Yang
` (2 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:11 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
Nowadays we allocate exception base from memblock for r2_r6,
so we don't need to reverse exception space at the start of
the memory for r2_r6 processors.
For older processors the reservation is moved to traps_init
where we have knowledge of exact size we need. We also add
a sanity check to detect possible overlap with kernel.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/traps.h | 1 -
arch/mips/kernel/cpu-probe.c | 5 -----
arch/mips/kernel/cpu-r3k-probe.c | 2 --
arch/mips/kernel/traps.c | 12 +++++++-----
4 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 15cde638b407..d3dddd1c083a 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,7 +24,6 @@ extern void (*board_ebase_setup)(void);
extern void (*board_cache_error_setup)(void);
extern int register_nmi_notifier(struct notifier_block *nb);
-extern void reserve_exception_space(phys_addr_t addr, unsigned long size);
extern char except_vec_nmi[];
#define VECTORSPACING 0x100 /* for EI/VI mode */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b406d8bfb15a..54e8b0fd4a2a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1570,7 +1570,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
c->cputype = CPU_BMIPS3300;
__cpu_name[cpu] = "Broadcom BMIPS3300";
set_elf_platform(cpu, "bmips3300");
- reserve_exception_space(0x400, VECTORSPACING * 64);
break;
case PRID_IMP_BMIPS43XX: {
int rev = c->processor_id & PRID_REV_MASK;
@@ -1581,7 +1580,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "Broadcom BMIPS4380";
set_elf_platform(cpu, "bmips4380");
c->options |= MIPS_CPU_RIXI;
- reserve_exception_space(0x400, VECTORSPACING * 64);
} else {
c->cputype = CPU_BMIPS4350;
__cpu_name[cpu] = "Broadcom BMIPS4350";
@@ -1598,7 +1596,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "Broadcom BMIPS5000";
set_elf_platform(cpu, "bmips5000");
c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
- reserve_exception_space(0x1000, VECTORSPACING * 64);
break;
}
}
@@ -1996,8 +1993,6 @@ void cpu_probe(void)
if (cpu == 0)
__ua_limit = ~((1ull << cpu_vmbits) - 1);
#endif
-
- reserve_exception_space(0, 0x1000);
}
void cpu_report(void)
diff --git a/arch/mips/kernel/cpu-r3k-probe.c b/arch/mips/kernel/cpu-r3k-probe.c
index be93469c0e0e..05410b743e57 100644
--- a/arch/mips/kernel/cpu-r3k-probe.c
+++ b/arch/mips/kernel/cpu-r3k-probe.c
@@ -137,8 +137,6 @@ void cpu_probe(void)
cpu_set_fpu_opts(c);
else
cpu_set_nofpu_opts(c);
-
- reserve_exception_space(0, 0x400);
}
void cpu_report(void)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 651c9ec6265a..b6e94654f621 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2007,10 +2007,6 @@ unsigned long exception_handlers[32];
static unsigned long vi_vecbase;
unsigned long vi_handlers[64];
-void reserve_exception_space(phys_addr_t addr, unsigned long size)
-{
- memblock_reserve(addr, size);
-}
void __init *set_except_vector(int n, void *addr)
{
@@ -2394,7 +2390,13 @@ void __init trap_init(void)
}
if (!cpu_has_mips_r2_r6) {
- ebase = CAC_BASE;
+ ebase_pa = 0x0;
+ ebase = CKSEG0ADDR(ebase_pa);
+
+ if (__pa_symbol(_stext) < (ebase_pa + vec_size))
+ pr_err("Insufficient space for exception vectors\n");
+
+ memblock_reserve(ebase_pa, vec_size);
} else {
vec_size = max(vec_size, PAGE_SIZE);
ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 09/10] MIPS: traps: Enhance memblock ebase allocation process
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
` (7 preceding siblings ...)
2023-10-27 22:11 ` [PATCH v2 08/10] MIPS: Avoid unnecessary reservation of exception space Jiaxun Yang
@ 2023-10-27 22:11 ` Jiaxun Yang
2023-10-27 22:11 ` [PATCH v2 10/10] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Jiaxun Yang
2023-11-08 16:12 ` [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Gregory CLEMENT
10 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:11 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
We try to allocate from KSEG0 accessible space first, and
then if we really can't allocate any memory from KSEG0 and
we are sure that we support ebase in higher segment, give
it another go without restriction.
This can maximize the possibility of having ebase in KSEG0.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/traps.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b6e94654f621..68f1dd54cde1 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2399,7 +2399,12 @@ void __init trap_init(void)
memblock_reserve(ebase_pa, vec_size);
} else {
vec_size = max(vec_size, PAGE_SIZE);
- ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
+ ebase_pa = memblock_phys_alloc_range(vec_size, 1 << fls(vec_size),
+ 0x0, KSEGX_SIZE - 1);
+
+ if (!ebase_pa && (IS_ENABLED(CONFIG_EVA) || cpu_has_ebase_wg))
+ ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
+
if (!ebase_pa)
panic("%s: Failed to allocate %lu bytes align=0x%x\n",
__func__, vec_size, 1 << fls(vec_size));
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 10/10] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
` (8 preceding siblings ...)
2023-10-27 22:11 ` [PATCH v2 09/10] MIPS: traps: Enhance memblock ebase allocation process Jiaxun Yang
@ 2023-10-27 22:11 ` Jiaxun Yang
2023-11-08 16:12 ` [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Gregory CLEMENT
10 siblings, 0 replies; 20+ messages in thread
From: Jiaxun Yang @ 2023-10-27 22:11 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, tsbogend, gregory.clement, vladimir.kondratiev,
Jiaxun Yang
NO_EXCEPT_FILL is used to indicate platform that does not
need to reserve ebase memory at start of kernel.
This is true for all R2+ platform as they allocate ebase
memory on fly, and also true for any platform that does
not load kernel at start of physical memory.
Get rid this Kconfig symbol by use macro to detect conditions
above.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 9 ---------
arch/mips/kernel/head.S | 7 +++++--
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bfedc8b48a81..e928ebc2cd1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -149,7 +149,6 @@ config MIPS_GENERIC_KERNEL
select MIPS_CPU_SCACHE
select MIPS_GIC
select MIPS_L1_CACHE_SHIFT_7
- select NO_EXCEPT_FILL
select PCI_DRIVERS_GENERIC
select SMP_UP if SMP
select SWAP_IO_SPACE
@@ -210,7 +209,6 @@ config AR7
select CEVT_R4K
select CSRC_R4K
select IRQ_MIPS_CPU
- select NO_EXCEPT_FILL
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
@@ -265,7 +263,6 @@ config BMIPS_GENERIC
select ARCH_HAS_RESET_CONTROLLER
select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
select BOOT_RAW
- select NO_EXCEPT_FILL
select USE_OF
select CEVT_R4K
select CSRC_R4K
@@ -309,7 +306,6 @@ config BCM47XX
select HAVE_PCI
select IRQ_MIPS_CPU
select SYS_HAS_CPU_MIPS32_R1
- select NO_EXCEPT_FILL
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MIPS16
@@ -445,7 +441,6 @@ config LANTIQ
select IRQ_MIPS_CPU
select CEVT_R4K
select CSRC_R4K
- select NO_EXCEPT_FILL
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_BIG_ENDIAN
@@ -494,7 +489,6 @@ config MACH_LOONGSON64
select ISA
select I8259
select IRQ_MIPS_CPU
- select NO_EXCEPT_FILL
select NR_CPUS_DEFAULT_64
select USE_GENERIC_EARLY_PRINTK_8250
select PCI_DRIVERS_GENERIC
@@ -1177,9 +1171,6 @@ config PCI_GT64XXX_PCI0
config PCI_XTALK_BRIDGE
bool
-config NO_EXCEPT_FILL
- bool
-
config MIPS_SPRAM
bool
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index b825ed4476c7..4af53b1628f5 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -59,10 +59,13 @@
#endif
.endm
-#ifndef CONFIG_NO_EXCEPT_FILL
+#if (MIPS_ISA_REV < 2) && \
+ ((VMLINUX_LOAD_ADDRESS == KSEG0) || \
+ (VMLINUX_LOAD_ADDRESS == CKSEG0))
/*
* Reserved space for exception handlers.
- * Necessary for machines which link their kernels at KSEG0.
+ * Necessary for machines which link their kernels at KSEG0
+ * and incapable of moving ebase.
*/
.fill 0x400
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS
2023-10-27 22:10 [PATCH v2 00/10] MIPS: Fix kernel in XKPHYS Jiaxun Yang
` (9 preceding siblings ...)
2023-10-27 22:11 ` [PATCH v2 10/10] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Jiaxun Yang
@ 2023-11-08 16:12 ` Gregory CLEMENT
10 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2023-11-08 16:12 UTC (permalink / raw)
To: Jiaxun Yang, linux-mips
Cc: linux-kernel, tsbogend, vladimir.kondratiev, Jiaxun Yang
Hello Jiaxun,
> Hi all,
>
> This series fixes support for loading kernel to XKPHYS space.
> It is derived from "MIPS: use virtual addresses from xkphys for MIPS64" [1].
>
Thanks for this new series, I was able to test it this week and I have a
few comments.
> Boot tested on boston and QEMU with loading address set to 0xa800000090000000.
> QEMU patch on the way.
>
> For EyeQ5's memory layout, I think you just need to write devicetree memory
> node as:
>
> memory@0 {
> device_type = "memory";
> reg = < 0x0 0x08000000 0x0 0x08000000
> 0x8 0x08000000 0x0 0x78000000>;
> };
>
> And set kernel load addesss to somewhere in RAM, everything should
> work.
With this setup and a workaround that I had to do and I will comment in
for the patch "MIPS: Refactor mips_cps_core_entry implementation", I
managed to boot the kernel and the 8 core of my setup are detected.
>
> It makes me a little bit confused that in EyeQ5 enablement patch, you set
> load address to:
>> +else
>> +load-$(CONFIG_MIPS_GENERIC) += 0xa800000080100000
>> +endif
> Where does not have memory aviailable.
>
> I guess you might want to set it to 0xa800000800100000?
> Though I would suggest you to set it to 0xa800000808000000, to avoid
> collisions with low mem and reserved mem.
Indeed I used CONFIG_PHYSICAL_START=0xa800000808000000
Gregory
>
> Gregory and Vladimir, do let me know if I missed anything.
>
> Thanks
> - Jiaxun
>
> [1]: https://lore.kernel.org/lkml/20231004161038.2818327-3-gregory.clement@bootlin.com/
>
> Jiaxun Yang (10):
> MIPS: Export higher/highest relocation functions in uasm
> MIPS: spaces: Define a couple of handy macros
> MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
> MIPS: Fix set_uncached_handler for ebase in XKPHYS
> MIPS: Refactor mips_cps_core_entry implementation
> MIPS: Allow kernel base to be set from Kconfig for all platforms
> MIPS: traps: Handle CPU with non standard vint offset
> MIPS: Avoid unnecessary reservation of exception space
> MIPS: traps: Enhance memblock ebase allocation process
> MIPS: Get rid of CONFIG_NO_EXCEPT_FILL
>
> arch/mips/Kconfig | 27 ++--
> arch/mips/include/asm/addrspace.h | 5 +
> arch/mips/include/asm/mach-generic/spaces.h | 5 +-
> arch/mips/include/asm/mips-cm.h | 1 +
> arch/mips/include/asm/smp-cps.h | 4 +-
> arch/mips/include/asm/traps.h | 1 -
> arch/mips/include/asm/uasm.h | 2 +
> arch/mips/kernel/cps-vec.S | 110 +++++--------
> arch/mips/kernel/cpu-probe.c | 5 -
> arch/mips/kernel/cpu-r3k-probe.c | 2 -
> arch/mips/kernel/genex.S | 19 ++-
> arch/mips/kernel/head.S | 7 +-
> arch/mips/kernel/smp-cps.c | 167 +++++++++++++++++---
> arch/mips/kernel/traps.c | 85 +++++++---
> arch/mips/mm/uasm.c | 6 +-
> 15 files changed, 293 insertions(+), 153 deletions(-)
>
> --
> 2.34.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 20+ messages in thread