From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF5BAC432BE for ; Wed, 25 Aug 2021 09:07:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B833B61184 for ; Wed, 25 Aug 2021 09:07:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233117AbhHYJH5 convert rfc822-to-8bit (ORCPT ); Wed, 25 Aug 2021 05:07:57 -0400 Received: from mail.kernel.org ([198.145.29.99]:47154 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232454AbhHYJH4 (ORCPT ); Wed, 25 Aug 2021 05:07:56 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 28534610CD; Wed, 25 Aug 2021 09:07:11 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mIosH-0076D7-63; Wed, 25 Aug 2021 10:07:09 +0100 Date: Wed, 25 Aug 2021 10:07:08 +0100 Message-ID: <87o89lq4eb.wl-maz@kernel.org> From: Marc Zyngier To: Kunihiko Hayashi Cc: Pali =?UTF-8?B?Um9ow6Fy?= , Lorenzo Pieralisi , Rob Herring , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Bjorn Helgaas , Masami Hiramatsu , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI: uniphier: Serialize INTx masking/unmasking In-Reply-To: References: <1629717500-19396-1-git-send-email-hayashi.kunihiko@socionext.com> <20210823150927.jhobzfxy6e4s663r@pali> <87zgt8p09n.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: hayashi.kunihiko@socionext.com, pali@kernel.org, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, bhelgaas@google.com, mhiramat@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 25 Aug 2021 01:01:08 +0100, Kunihiko Hayashi wrote: > > Hi Marc, > > On 2021/08/24 1:57, Marc Zyngier wrote: > > On Mon, 23 Aug 2021 16:09:27 +0100, > > Pali Rohár wrote: > >> > >> + Marc (who originally reported this issue) > >> > >> On Monday 23 August 2021 20:18:20 Kunihiko Hayashi wrote: > >>> The condition register PCI_RCV_INTX is used in irq_mask(), irq_unmask() > >>> and irq_ack() callbacks. Accesses to register can occur at the same time > >>> without a lock. > >>> Add a lock into each callback to prevent the issue. > >>> > >>> Fixes: 7e6d5cd88a6f ("PCI: uniphier: Add UniPhier PCIe host controller support") > >>> Suggested-by: Pali Rohár > >>> Signed-off-by: Kunihiko Hayashi > >> > >> Acked-by: Pali Rohár > >> > >>> --- > >>> drivers/pci/controller/dwc/pcie-uniphier.c | 15 +++++++++++++++ > >>> 1 file changed, 15 insertions(+) > >>> > >>> The previous patch is as follows: > >>> https://lore.kernel.org/linux-pci/1629370566-29984-1-git-send-email-hayashi.kunihiko@socionext.com/ > >>> > >>> Changes in the previous patch: > >>> - Change the subject and commit message > >>> > >>> diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c > >>> index ebe43e9..5075714 100644 > >>> --- a/drivers/pci/controller/dwc/pcie-uniphier.c > >>> +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > >>> @@ -186,12 +186,17 @@ static void uniphier_pcie_irq_ack(struct irq_data *d) > >>> struct pcie_port *pp = irq_data_get_irq_chip_data(d); > >>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > >>> struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); > >>> + unsigned long flags; > >>> u32 val; > >>> + raw_spin_lock_irqsave(&pp->lock, flags); > >>> + > >>> val = readl(priv->base + PCL_RCV_INTX); > >>> val &= ~PCL_RCV_INTX_ALL_STATUS; > >>> val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT); > >>> writel(val, priv->base + PCL_RCV_INTX); > >>> + > >>> + raw_spin_unlock_irqrestore(&pp->lock, flags); > >>> } > >>> static void uniphier_pcie_irq_mask(struct irq_data *d) > >>> @@ -199,12 +204,17 @@ static void uniphier_pcie_irq_mask(struct irq_data *d) > >>> struct pcie_port *pp = irq_data_get_irq_chip_data(d); > >>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > >>> struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); > >>> + unsigned long flags; > >>> u32 val; > >>> + raw_spin_lock_irqsave(&pp->lock, flags); > >>> + > >>> val = readl(priv->base + PCL_RCV_INTX); > >>> val &= ~PCL_RCV_INTX_ALL_MASK; > >>> val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); > > > > This looks extremely suspicious. You clear all the INTX mask bits, and > > only set the one you need. How about the pre-existing bits? > > Thanks for pointing out. No need to clear all INTX mask bits. > The pre-existing bits should be preserved. > > > > >>> writel(val, priv->base + PCL_RCV_INTX); > >>> + > >>> + raw_spin_unlock_irqrestore(&pp->lock, flags); > >>> } > >>> static void uniphier_pcie_irq_unmask(struct irq_data *d) > >>> @@ -212,12 +222,17 @@ static void uniphier_pcie_irq_unmask(struct irq_data *d) > >>> struct pcie_port *pp = irq_data_get_irq_chip_data(d); > >>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > >>> struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); > >>> + unsigned long flags; > >>> u32 val; > >>> + raw_spin_lock_irqsave(&pp->lock, flags); > >>> + > >>> val = readl(priv->base + PCL_RCV_INTX); > >>> val &= ~PCL_RCV_INTX_ALL_MASK; > >>> val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); > > > > And by the same token, this second line is totally useless. > > > > I think masking/unmasking is broken in this driver, locking or not. > > Yes, this second line should be removed, too. You mean the *first* line, right? The one clearing all the INTx bits. If you remove the second line, you won't fix anything. Thanks, M. -- Without deviation from the norm, progress is not possible.