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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id c8sm24438550wru.7.2020.03.03.05.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2020 05:38:30 -0800 (PST) From: Vitaly Kuznetsov To: Paolo Bonzini Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Oliver Upton Subject: Re: [GIT PULL] KVM changes for Linux 5.6-rc4 In-Reply-To: <9bb75cdc-961e-0d83-0546-342298517496@redhat.com> References: <1582570669-45822-1-git-send-email-pbonzini@redhat.com> <87zhcyfvmk.fsf@vitty.brq.redhat.com> <8fbeb3c2-9627-bf41-d798-bafba22073e3@redhat.com> <87tv35fv5t.fsf@vitty.brq.redhat.com> <9bb75cdc-961e-0d83-0546-342298517496@redhat.com> Date: Tue, 03 Mar 2020 14:38:29 +0100 Message-ID: <87o8tdftii.fsf@vitty.brq.redhat.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Paolo Bonzini writes: > On 03/03/20 14:02, Vitaly Kuznetsov wrote: >> Right you are, >> >> a big hammer like >> >> diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h >> index 2a8f2bd..52c9bce 100644 >> --- a/arch/x86/include/asm/kvm_emulate.h >> +++ b/arch/x86/include/asm/kvm_emulate.h >> @@ -324,14 +324,6 @@ struct x86_emulate_ctxt { >> */ >> >> /* current opcode length in bytes */ >> - u8 opcode_len; >> - u8 b; >> - u8 intercept; >> - u8 op_bytes; >> - u8 ad_bytes; >> - struct operand src; >> - struct operand src2; >> - struct operand dst; >> union { >> int (*execute)(struct x86_emulate_ctxt *ctxt); >> fastop_t fop; >> @@ -343,6 +335,14 @@ struct x86_emulate_ctxt { >> * or elsewhere >> */ >> bool rip_relative; >> + u8 opcode_len; >> + u8 b; >> + u8 intercept; >> + u8 op_bytes; >> + u8 ad_bytes; >> + struct operand src; >> + struct operand src2; >> + struct operand dst; >> u8 rex_prefix; >> u8 lock_prefix; >> u8 rep_prefix; >> >> seems to make the issue go away. (For those wondering why fielf >> shuffling makes a difference: init_decode_cache() clears >> [rip_relative, modrm) range) How did this even work before... >> (I'm still looking at the code, stay tuned...) > > On AMD, probably because all these instructions were normally trapped by L1. > > Of these, however, most need not be zeroed again. op_bytes, ad_bytes, > opcode_len and b are initialized by x86_decode_insn, and dst/src/src2 > also by decode_operand. So only intercept is affected, adding > "ctxt->intercept = x86_intercept_none" should be enough. This matches my findings, thank you! Patch[es] are coming. -- Vitaly