From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EC0F16FF37 for ; Tue, 7 Apr 2026 08:40:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775551222; cv=none; b=cIoiUTaeBEDBAjj3jKfd8MSfTpXQdNBBlXQmg1s54UqFpJbFWqh7+sxizoGrJl5RuHBDaNnRG+4MHrEikrPnwZwECa8fR96h+l/qB66+GpqrlQgNWc9+L+x4F+TAIKcx552OVpQzbnpqFUWxxIn1kLX8B/xDf3FVLMBoFTx9ONc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775551222; c=relaxed/simple; bh=5grt+gVOxEdjprjHIApzhtZ5oJSzpHJg2yf0qrKuaKA=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=N6nDIXHBgyrT2kfIoF1Ug9oyhir30vNdmIDtasFguYjHw3ck9qXU89MBQxJ2TrhPU37ZLEte6TM42XHy5evuG12BLysTt/3WX50kx+vG6m3g7+1RVeFHM5yaf9QBWXWj5fjmAcF/pwua4pmCzhO0/SulOnOeLkBOFrUXtJJIQTg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=q+BYRs/6; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=tQZ6/KOg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="q+BYRs/6"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="tQZ6/KOg" From: Nam Cao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1775551217; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=3P6sppRCZ532nysjXQBZ63OmSOENOJ3gK1ZnNiYlpPk=; b=q+BYRs/6LyZS484YvYqzyuGbHATpi84PID9SKYhbvA40mfLLH0r8YQjwWPdvqdPRgqF4qR uL5LNmdjAc0Wordcc5bh4E5mJAAXmhH++wpfkxBu3JWHgeTnvAStxyeyeXLDzDspIWXDOC q4uoHaXn8k5eZq4EvitInM5M5B5i/0WatI4AWVeFSv1+q2jfs4+pHVY62fwWQqJ0It6F45 KLZnWDox8Xclw6Wrc/BsgnvzeLr1GN3g9WvO6+S49V1rWDouvN7ixv1om5of8AifT9ovtN uB6q3id5k3tAWMko427kBAkQ4oErNZYVUQ8hfAfEmfQ6xwuyx3FcMYjGG8SJHw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1775551217; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=3P6sppRCZ532nysjXQBZ63OmSOENOJ3gK1ZnNiYlpPk=; b=tQZ6/KOgxlfpxOcdBdbkzz0fEFFuJxOFWFN32mUoIjcJ7zsDQ/WCe85CxMJNpSpff4GDHd IOEa1g2h3A3VumAQ== To: Adriano Vero , palmer@dabbelt.com, pjw@kernel.org, aou@eecs.berkeley.edu Cc: alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Adriano Vero Subject: Re: [PATCH] riscv: Add WFI to secondary hart spinwait loop In-Reply-To: <20260407074534.59179-1-litaliano00.contact@gmail.com> References: <20260407074534.59179-1-litaliano00.contact@gmail.com> Date: Tue, 07 Apr 2026 10:40:17 +0200 Message-ID: <87pl4bw4cu.fsf@yellow.woof> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Adriano Vero writes: > The .Lwait_for_cpu_up loop in the RISCV_BOOT_SPINWAIT path busy-polls > __cpu_spinwait_stack_pointer and __cpu_spinwait_task_pointer, burning > power on all non-boot harts while they wait for the primary hart to > complete early boot setup. > > Add a WFI instruction before each polling iteration to allow the > hardware to enter a low-power state while waiting. Per the RISC-V > privileged specification, WFI wakes on any pending interrupt even > with global interrupts disabled (SIE=0), and implementations are > permitted to treat it as a NOP, so this is safe in all contexts. > > The same pattern is already used in .Lsecondary_park in the same > file. > > Signed-off-by: Adriano Vero > --- > arch/riscv/kernel/head.S | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index 9c99c5ad6..ca208da7c 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -385,7 +385,14 @@ SYM_CODE_START(_start_kernel) > * get far enough along the boot process that it should continue. > */ > .Lwait_for_cpu_up: > - /* FIXME: We should WFI to save some energy here. */ > + /* > + * Wait for the boot hart to populate the stack and task pointers. > + * Use WFI to avoid burning power in a busy-wait loop. Per the > + * RISC-V privileged spec, WFI wakes on a pending interrupt even > + * with global interrupts disabled (e.g. SIE=0), and implementations > + * are permitted to treat it as a NOP, so this is always safe. > + */ > + wfi > REG_L sp, (a1) > REG_L tp, (a2) > beqz sp, .Lwait_for_cpu_up > -- > 2.53.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv