From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA01F3A3E82 for ; Mon, 30 Mar 2026 14:22:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774880545; cv=none; b=Y/drtYsXkj0j1uPwTAgKdmVQf+I8MDxMBc+Ngn2FuJwcz6OcrWaHIRB8XSyVo+9i0IMD+0va4yCiQg03QDalP8EDBoYE4W8snz4tuKqeIOBLLFHzdj2A2O86MtQe5RTouyr1SeI0I4I/PwpDxPEtOj4KfPobudXeE7ohh5jzunw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774880545; c=relaxed/simple; bh=CMlkOcsIWyHdi0qofuXqXjRXwjrRocpNDJSfVKXajYA=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=iQKAKYOJhZjBrtZIIxW7k6COgUPau2S/SdhQZNSS/Z1+ybWfpi8gnCLSwDx++E9b9Be4hjfqXQQ4wEGOZU8Nbw8fRzT5GLDnAR/6NVCE3ATuP8OqA+kZvl2iMfl0AFC0fiOBcPgJTNuKfNKRoXpg/FFixvzf8vHsYxs07397ByE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=OcOy7g0C; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="OcOy7g0C" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id AAB434E427BA; Mon, 30 Mar 2026 14:22:19 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 7E8B25FFA8; Mon, 30 Mar 2026 14:22:19 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7685710450520; Mon, 30 Mar 2026 16:22:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1774880539; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=P+TOHPnqWTS0+au25Q+Iw6/W1cExbaPQRvs67MI09EA=; b=OcOy7g0CWYr8YyU+iP0AYmitw4QOsaWzpQNIlQqdMW0+aAynROjsjF6WkdOqyOgxXVL/q9 f/CumuY9K0NYhFbGeuWvx+2H4b7DO1F17ET/RYj7e9E9FpgA+vmzBZyhgbjK8DzLDMz35n V6twMyhQkkSWcSt7I15YwqGpjqOm5X4iodNw6bx/r/hJDTH6FuyH/z0iw92N73TYc0bZe7 T6PKjvLCT0NB2hSxIZQ03oAwvDrEOkjmfQZE2d0112/KsQAXFRmqpSWp+HjWz1zZOYttzX e6aPGGiRKOZxOSkLbyKVvFRxghxomo9TRh25dpM27ycM7GKotgAxQTvxo0uqRg== From: Miquel Raynal To: Pratyush Yadav Cc: Eliav Farber , , , , , , Subject: Re: [PATCH v2 0/3] mtd: spi-nor: winbond: Fix protection handling In-Reply-To: <2vxzcy0l1k7g.fsf@kernel.org> (Pratyush Yadav's message of "Mon, 30 Mar 2026 14:10:59 +0000") References: <20260218143523.17467-1-farbere@amazon.com> <2vxzcy0l1k7g.fsf@kernel.org> User-Agent: mu4e 1.12.7; emacs 30.2 Date: Mon, 30 Mar 2026 16:22:15 +0200 Message-ID: <87pl4l9z3c.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 >> The devices do not correctly describe their Status Register layout and >> protection capabilities (locking flags, TB bit, BP bit configuration). >> As a result, the spi-nor core rejects protection requests and locking >> operations fail with -EINVAL, e.g.: >> >> flash_lock -l /dev/mtd29 >> flash_lock: error!: could not lock device: /dev/mtd29 >> error 22 (Invalid argument) >> >> Update the device flags to match the actual hardware behavior so that >> locking and unlocking regions work correctly. >> >> All changes were validated using flash_lock on the affected devices. > > Applied patches 1 and 3 to spi-nor/next. Thanks! > > Skipped patch 2 since you say that you haven't got a device to test > with. I don't have a very strong opinion on this, but I do think we > should test patches on real hardware just to we get some sanity checking > for the patch. Honestly, I am pretty convinced patch 2 cannot make more harm as the block protection is already badly broken by not being described at all. Furthermore, for similar chips I have, these bits are relevant, so I would rather be in favour of going forward with patch 2, because at most it will just not fix the behaviour as it pretends it does. My 2cts :) Miqu=C3=A8l