From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64EFB364EBE for ; Fri, 13 Mar 2026 08:07:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773389275; cv=none; b=McFlouzR6zeL4KfUVwql1BU8jqSbtAykoiWZa/a3lZKfWh5CXQZkkBd0ROAL6OTGlS+v+vvtJ0rRIG9DeKFpopdo1ArZ6GPxbZZAvqokCt90sJ2f6Hnr7U4GzAFT6Ztu2+qg/JHPaxa94r6YJH8l9uUiGPAqucg4ktEIkVeEUJ4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773389275; c=relaxed/simple; bh=ODWFk73CHcFmSLAadPfMCSjy+h/1PZURDy8CTdcGFdU=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=bNstkNEZlNi3a6bChX72AMs9Y8LNfDngBm1zHrLS3ITsBZB1jZ/5WfTtEALzmmp5TnXYlBp12CQPw1wpbnOvs50QZ/hVJPhL0rix4Aqc0C1phrLMGjzstyc/gV4dkcbnRLpY6+EJ2LHSTOH8D2/XLpnCIQhB1XSaZzwK4pIji3M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=M2KuIDnJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M2KuIDnJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00194C19421; Fri, 13 Mar 2026 08:07:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773389275; bh=ODWFk73CHcFmSLAadPfMCSjy+h/1PZURDy8CTdcGFdU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=M2KuIDnJ2Ab4omaPCRDhzxgkq/j5C/KM4VyOPWdDxk+OAPxic2j6bFn7PKR4jJ2/v gDTgGzXVVJbiKbl0G1mkYHIFisHk3ZMkect4xCAWzF00Kxn0sp7FZXiXD4vd7s8xVk yZeYJIkf7eqB2qIP6p45WcK7fvSjjyl1mZdXncn3WR9N9bhJFpwEzON86yhZDK9Wzs /du5mdahT0iOOJJIGifhg9FfWKg1fg2xZ+fzv3OhMKmA6HihEh2rsky/sRkewaV3b1 GcNf71Szvl2kBsfGWpJTEXhF4r1rOYFSsacZqZGhBkulAALTeIgLV5Rnu1mI95pWcB vI/JdoZLjR3lg== Received: from 82-132-235-41.dab.02.net ([82.132.235.41] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w0xYm-00000001Zie-2UF2; Fri, 13 Mar 2026 08:07:52 +0000 Date: Fri, 13 Mar 2026 08:07:51 +0000 Message-ID: <87pl58cfu0.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Oliver Upton , Mark Rutland , linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2() In-Reply-To: References: <20260313053857.1277828-1-anshuman.khandual@arm.com> <87sea4chrw.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 82.132.235.41 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, oupton@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 13 Mar 2026 07:54:04 +0000, Anshuman Khandual wrote: > > On 13/03/26 12:55 PM, Marc Zyngier wrote: > > On Fri, 13 Mar 2026 05:38:57 +0000, > > Anshuman Khandual wrote: > >> > >> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which > >> ensures that MMU stage-2 translation remain disabled. Although clearing out > >> VTTBR_EL2 probably should have been sufficient but adding VTCR_EL2 improves > >> overall safety. > > > > This serves no purpose whatsoever. Even the write to VTTBR_EL2 is > > pointless, and writing 0 is no better than writing *any* other value. > > > The only thing that matters at this stage is HCR_EL2.VM, which > > actually controls stage-2 translation (contrary to your above > > assertion). This of course is not captured by this macro. > > > > So what are you *really* trying to achieve? > > To keep VTTBR_EL2 and VTCR_EL2 cleared (and prepared) if and when > HCR_EL2_VM gets enabled. How does that prepare anything? Zero is not even a valid value for VTCR_EL2! > But it can be argued that these registers > need not have to be cleared now and can just be initialised before > setting up HCR_EL2_VM itself. In which case should we drop > __init_el2_stage2() entirely ? I really like how you argue one thing and its opposite in two adjacent sentences. "If it ain't broke, don't fix it". M. -- Jazz isn't dead. It just smells funny.