From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41E7325A63A for ; Mon, 27 Jan 2025 10:33:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737974022; cv=none; b=BscwaXQ7u5I4OZK7+Q82U0i4VPsZrVpWzqTqlUexARtJwcPWDTJpttLP5HYY3yQgO/UGRmPHc6uaoeBDJCB9mExnHZk+z2oGYUd/XUhSr+uzpRmeB6y6hDS8xU6yw0vFGWjqJNlQY9wISCFmZIRou35NNgZflyl3F5OMGgPTmYk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737974022; c=relaxed/simple; bh=uQcNqnxtO/8BvqHLitjDdNhMKIMvRgEKjoKbeWNNyFE=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=IXL2wsyc3LnW4iwXJQ04XvO83meRkcCGp8omKVmA91EBpvud71VusnwGpizqGlv2pAolifVE4HqHAk+oXxQdj8fkzg1g72zXEMccvevIJyYjxlxk81Yj1LDAZXKxA/pvfIJYZCLgHU6cbw2K4SFDE6BEFPBJswDnE05x5YCaKy8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=AhFbn6lv; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=lCFGDASC; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="AhFbn6lv"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="lCFGDASC" From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1737974019; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=kz09BdGMPdqQP6LKhOKJr4faf/0LLBwoYDmVc+SBRyE=; b=AhFbn6lvifGljtiLo2IXEk5UIWHLLp3Ev7laKcHpnmSo3NRqn15gf2NeWdMODuNqj+RZW0 LuL7/PQl/YLIDZin1pm43feceGSQR1rP/D/5Oz113P+mjcr/mBlmTVq4D+z3jq1B3+D3i+ 4UjNea5nkbu2cs8ZCnzNc3zeeNUKf5c6OL3I07rQYnaDRxTGmKKNsbZe+VyUlIbE894rkC lIYpfk/Jt6RxTFMeu+IeSc2hh3Otr7eWyFOG4kbsG/fegwLCMFWUfZEUcFIwSERnJTmxym E6JLDU16r8+J0f4aekuio1FY+4WFx1pAJsKOMtEzkHW2HOzKvmS3yTbpRFtR0w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1737974019; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=kz09BdGMPdqQP6LKhOKJr4faf/0LLBwoYDmVc+SBRyE=; b=lCFGDASC/19nNForuhwI3jqWqkguIBX8vw8ClCmdkKxRw5HTRo+XehRPgK8oBe6WlJSQjt ITHhyT/VTBDNx6Aw== To: Xu Lu , anup@brainfault.org, charlie@rivosinc.com, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: Re: [PATCH RESEND] irqchip: riscv: Order normal writes and IPI writes In-Reply-To: <20250127093846.98625-1-luxu.kernel@bytedance.com> References: <20250127093846.98625-1-luxu.kernel@bytedance.com> Date: Mon, 27 Jan 2025 11:33:39 +0100 Message-ID: <87plk88s1o.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Mon, Jan 27 2025 at 17:38, Xu Lu wrote: This is not a RESEND. The change log has been modified, no? The prefix is incorrect. See https://www.kernel.org/doc/html/latest/process/maintainer-tip.html > RISC-V distinguishes between normal memory accesses and device I/O and What is a normal memory write? Are there abnormal memory writes too? > uses FENCE instruction to order them as viewed by othe RISC-V harts and > external devices or coprocessors. The FENCE instruction can order any > combination of device input(I), device output(O), memory reads(R) and > memory writes(W). For example, 'fence w, o' can be used to ensure all Can be? It _is_ used, no? > memory writes from instructions preceding the FENCE instruction appear > earlier in the global memory order than device output writes from > instructions after the FENCE instruction. > > RISC-V issues IPI by writing certain value to IMSIC/ACLINT MMIO > registers, which is regarded as device output operation. However, the > existing implementation of IMSIC/ACLINT driver issues IPI via > writel_relaxed(), which does not guarantee the order of device output > operation and preceding memory writes. Then the hart receiving IPI may > not have seen the latest data yet. > > This commit fixes this by replacing writel_relaxed() with writel() > when 'This commit' is equally wrong as 'This patch'. See Documentation/process/ > issuing IPI, which will use 'fence w, o' to ensure all previous writes > made by current hart are visible to other harts before they receive > the IPI. I've fixed it up for you. Thanks, tglx