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From:   =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
To:     Conor Dooley <conor.dooley@microchip.com>
Cc:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org, Andy Chiu <andy.chiu@sifive.com>,
        Greentime Hu <greentime.hu@sifive.com>,
        "Jason A . Donenfeld" <Jason@zx2c4.com>,
        Samuel Neves <sneves@dei.uc.pt>,
        =?utf-8?B?QmrDtnJu?= =?utf-8?B?IFTDtnBlbA==?= 
        <bjorn@rivosinc.com>, Heiko Stuebner <heiko@sntech.de>,
        Herbert Xu <herbert@gondor.apana.org.au>,
        "David S. Miller" <davem@davemloft.net>,
        linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 0/6] RISC-V BLAKE2s Vector implementation
In-Reply-To: <20230914-roaming-plunging-948c78d9831c@wendy>
References: <20230912115728.172982-1-bjorn@kernel.org>
 <20230914-roaming-plunging-948c78d9831c@wendy>
Date:   Thu, 14 Sep 2023 14:59:30 +0200
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Conor Dooley <conor.dooley@microchip.com> writes:

> On Tue, Sep 12, 2023 at 01:57:22PM +0200, Bj=C3=B6rn T=C3=B6pel wrote:
>> From: Bj=C3=B6rn T=C3=B6pel <bjorn@rivosinc.com>
>>=20
>> Hi,
>>=20
>> This is Andy's kernel mode vector V2 series [1], with my BLAKE2s
>> AVX-512-to-RISC-V translation patch appended.
>>=20
>> I've tagged it as RFC, since Andy's series is still not in-tree yet.
>>=20
>> It's a first step towards a Vector aided Wireguard! ;-)
>
> This has the same problems as Andy's stuff & doesn't build properly for t=
he
> automation. What is the plan between yourself and Andy for submitting a
> version of the in-kernel vector support that passes build testing?

I'll synch up with Andy! I'm not even sure the blake2s patch should part
of the "in-kernel vector" series at all.

Thanks,
Bj=C3=B6rn