From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 009E5C19F2A for ; Thu, 11 Aug 2022 09:49:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234306AbiHKJtm (ORCPT ); Thu, 11 Aug 2022 05:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229724AbiHKJtk (ORCPT ); Thu, 11 Aug 2022 05:49:40 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 979F583BE3 for ; Thu, 11 Aug 2022 02:49:38 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3D50D615CC for ; Thu, 11 Aug 2022 09:49:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 996EBC433C1; Thu, 11 Aug 2022 09:49:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660211377; bh=YW9t4kKo8pIBu8PhKH9NfMl2vSDZjv9hBf9+ipbEbKE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Yq5m4Jtau6ifbwRvn1cWvPREhqs5mVxPKc7MKKdoT7CtgSo6fUWdrzHqjBWzSPbpG JDuy52e+iJ5pyVDDhDkOL6DXsnCayNIuNBUDphkFV5NBKz4m1xOXVWLxnnmnBPftUb Ec1+VoRrEh5vJgWXBBUE2Gpdg2dYNGVVq3gakyFELoGr7CegsT69jSjIxeMHHDWNhh fFMVFuqju82Jz9j/ko8K992Yq+Ad6yQqQdt8bNyZ9IuJ7Go9g2z2shvvLckDZ4Kwoy jfKf3l36lvy66GtZCfBOUdpbAwcPR6AW44Yx3KmB4Fuo11zl2fTZduU9x2coY16v7a zVihbpm8ZBljQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oM4op-002JOX-B7; Thu, 11 Aug 2022 10:49:35 +0100 Date: Thu, 11 Aug 2022 10:49:35 +0100 Message-ID: <87pmh7un2o.wl-maz@kernel.org> From: Marc Zyngier To: Ayan Kumar Halder Cc: , , , , , , , , Subject: Re: [PATCH v1] arm: clocksource: Check if timer is enabled for timer irq In-Reply-To: <20220811093620.16680-1-ayankuma@amd.com> References: <20220811093620.16680-1-ayankuma@amd.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ayankuma@amd.com, stefano.stabellini@xilinx.com, sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 11 Aug 2022 10:36:20 +0100, Ayan Kumar Halder wrote: > > Refer ARM DDI 0487G.b, CNTP_CTL_EL0, > ISTATUS, bit [2] - When the value of the ENABLE bit is 1, ISTATUS > indicates whether the timer condition is met. > > Thus, one need to check ENABLE bit along with ISTATUS, to confirm > whether the timer condition is met. Further as the doc says, > "When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN." > > Signed-off-by: Ayan Kumar Halder > --- > > Please refer to https://lore.kernel.org/all/6cfcd4fa-3afd-1c70-6a70-9df557ee1811@xen.org/T/ > for the previous discussion on this issue on xen-devel mailing list. > > drivers/clocksource/arm_arch_timer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c > index 9ab8221ee3c6..96921772814c 100644 > --- a/drivers/clocksource/arm_arch_timer.c > +++ b/drivers/clocksource/arm_arch_timer.c > @@ -647,7 +647,7 @@ static __always_inline irqreturn_t timer_handler(const int access, > unsigned long ctrl; > > ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); > - if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { > + if ((ctrl & ARCH_TIMER_CTRL_IT_STAT) && (ctrl & ARCH_TIMER_CTRL_ENABLE)) { > ctrl |= ARCH_TIMER_CTRL_IT_MASK; > arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); > evt->event_handler(evt); And how can the timer be disabled if we're in the interrupt handler? M. -- Without deviation from the norm, progress is not possible.