From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 081B1C433EF for ; Wed, 8 Jun 2022 07:04:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240232AbiFHHDq (ORCPT ); Wed, 8 Jun 2022 03:03:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354117AbiFHGSq (ORCPT ); Wed, 8 Jun 2022 02:18:46 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44D5071A35; Tue, 7 Jun 2022 23:05:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D055B617A1; Wed, 8 Jun 2022 06:05:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 287FEC34116; Wed, 8 Jun 2022 06:05:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654668355; bh=P2zL5dkPt1x7a+y6iwwy42Em2eZSX58H1IJ8uo2sTGo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=h68tVMBb7Q/vvcZc6G95rDZtISmbP1MxLXKrk3skaVLBr+e1MNbWc5Va9J+F5lqmN 7XG5VPoWPAg+g2BtnKTp8RuJQUdVqgxdabOOsPfVrGpCMWB43hNn2KW1G054upwkyc OvvcEf/wmrhsRIPFtKb1x+ZPR9AbzEt1QxUIbJkZiimCsTgNKvoPZBb5TqmYi9l8xO dPQ2Ur3gx7QlOl1aoS8SPvGzR4J3vSIRWd++hE7rF0I6H604MlLoyIJEH5ItwmRkIb owDnG18a4sqINmz0uHmc7NMWTFb6nH8awGcnsYbPDSAaGcCMFUsQd21k9Jp1hHZuHp g9zk1py7cI08Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nyopE-00GVfm-KW; Wed, 08 Jun 2022 07:05:52 +0100 Date: Wed, 08 Jun 2022 07:05:51 +0100 Message-ID: <87pmjjzo3k.wl-maz@kernel.org> From: Marc Zyngier To: Jiaxun Yang Cc: Dragan Mladjenovic , Thomas Bogendoerfer , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang Subject: Re: [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support In-Reply-To: <0a5dd632-0607-dab6-4de7-1ea248490863@flygoat.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> <20220525121030.16054-7-Dragan.Mladjenovic@syrmia.com> <87wndu3tff.wl-maz@kernel.org> <0a5dd632-0607-dab6-4de7-1ea248490863@flygoat.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jiaxun.yang@flygoat.com, Dragan.Mladjenovic@syrmia.com, tsbogend@alpha.franken.de, cfu@wavecomp.com, daniel.lezcano@linaro.org, geert@linux-m68k.org, gerg@kernel.org, hauke@hauke-m.de, ilya.lipnitskiy@gmail.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, paulburton@kernel.org, peterz@infradead.org, fancer.lancer@gmail.com, tglx@linutronix.de, yangtiezhu@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 07 Jun 2022 19:23:02 +0100, Jiaxun Yang wrote: >=20 >=20 >=20 > =E5=9C=A8 2022/6/6 12:47, Marc Zyngier =E5=86=99=E9=81=93: > > On Wed, 25 May 2022 13:10:24 +0100, > > Dragan Mladjenovic wrote: > >> From: Paul Burton > >>=20 > >> The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept = of > >> multiple clusters to the system. In these systems each cluster contains > >> its own GIC, so the GIC isn't truly global any longer. We do have the > >> ability to access registers in the GICs of remote clusters using a > >> redirect register block much like the redirect register blocks provided > >> by the CM & CPC, and configured through the same GCR_REDIRECT register > >> that we our mips_cm_lock_other() abstraction builds upon. > >>=20 > >> It is expected that external interrupts are connected identically to a= ll > >> clusters. That is, if we have a device providing an interrupt connected > >> to GIC interrupt pin 0 then it should be connected to pin 0 of every G= IC > >> in the system. This simplifies things somewhat by allowing us for the > >> most part to treat the GIC as though it is still truly global, so long > >> as we take care to configure interrupts in the cluster that we want th= em > >> affine to. > > I can see how this can work for level interrupts, but how does this > > work for edge interrupts? Is there any guarantee that the interrupt > > will be discarded if routed to a cluster where it isn't configured? > It is supposed to mask the interrupt out on the GIC which belongs to the > cluster that the interrupt is not routed to. >=20 > When it's masked out GIC simply won't sense any level change. >=20 > I guess it's sort of guarantee? Pretty much the opposite. There is a *strong* requirement that a masked interrupt can still detect interrupts, so that on unmask the interrupt fires (you'd otherwise lose edge interrupts pretty often). What does the MIPS GIC arch spec says about this? Thanks, M. --=20 Without deviation from the norm, progress is not possible.