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Wed, 4 Apr 2018 02:05:29 -0400 Received: from mga06.intel.com ([134.134.136.31]:28373 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750890AbeDDGF2 (ORCPT ); Wed, 4 Apr 2018 02:05:28 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,405,1517904000"; d="scan'208";a="188497261" From: Felipe Balbi To: Masahiro Yamada Cc: linux-usb@vger.kernel.org, Lee Jones , Arnd Bergmann , Rob Herring , devicetree@vger.kernel.org, Andrew Lunn , Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi , Linux Kernel Mailing List , Mathias Nyman Subject: Re: Multiple generic PHY instances for DWC3 USB IP In-Reply-To: References: <87vad7cz2i.fsf@linux.intel.com> Date: Wed, 04 Apr 2018 09:04:43 +0300 Message-ID: <87po3fcxs4.fsf@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-usb-owner@vger.kernel.org X-Mailing-List: linux-usb@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Hi, Masahiro Yamada writes: > 2018-04-04 14:36 GMT+09:00 Felipe Balbi : >> >> Hi, >> >> Masahiro Yamada writes: >>> Currently, DWC3 core IP (drivers/usb/dwc3/core.c) >>> can take only one PHY phandle for each of SS, HS. >>> (phy-names DT property is "usb2-phy" and "usb3-phy" for each) >> >> We never had any other requirements :-) >> >>> The DWC3 core IP is provided by Synopsys, >>> but some SoC-dependent parts (a.k.a glue-layer) >>> are implemented by SoC venders. >>> >>> The number of connected PHY instances are SoC-dependent. >>> >>> If you look at generic drivers such as >>> drivers/usb/host/ehci-platform.c >>> the driver can handle arbitrary number of PHY instances. >>> >>> However, as mentioned above, DWC3 core allows only one PHY phandle >>> for each SS/HS. >>> This can result in a strange DT structure. >>> >>> For example, Socionext PXs3 SoC is integrated with 2 instances of DWC3. >>> >>> The instance 0 of DWC3 is connected with 2 super-speed PHYs. >> >> why 2 super-speed phys? Is this a two-port host-only implementation? > > > Socionext SoCs only support the host-mode. > > > The instance 0 has 2 ports. > In our integration, 1 SS PHY is needed for each port. > That's why it needs 2 SS PHYs. > > Each DWC3 instance is connected with > multiple HS PHYs and multiple SS PHYs, > depending on the number of ports. in that case, you shouldn't need dwc3 at all. A Host-only dwc3 is xHCI compliant. If you really don't have the gadget block, there's no need for you to use dwc3. Just use xhci-plat directly. >>> Is this OK? >> >> I don't know, I need a bit more details about your integration :-) > > > I can send a patch. > > My concern is the following commit. > I do not know which parts are using this lookups. Samsung SoCs, probably ;-) Anyway, if your IP really is host-only, then you don't need dwc3 for anything. Just go for xHCI directly. If xHCI needs to be extended when it comes to PHY, then you can discuss with Mathias Nyman :-) -- balbi