From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA11D37204E for ; Mon, 10 Aug 2026 07:58:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786348721; cv=none; b=PcoGsSbY9Z/TrMsJG7SCg130D/gb3wq4pcEJ5LqvpfjigHkqYiWKWhDcfiEVbGTBJW3jxw1oTkUsS1BvPR8Yt4c7r1I3FkJpR6W/+A5D8bi62QZRE+NPRACth1Ko6NmpuDUjbNxkn7fGls1oID565BXGrf28BK1pGKkrKwoFTy8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786348721; c=relaxed/simple; bh=vj06TEBnL4aPmPsWUEUUxZCFLII1PgImt+SYyygUHVQ=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=c0VafSn+VqsCCAWQ4p6J5HtHDUHVzD4y22CBrUfi54HOWiMcW20ReCqvqvV2PWjqksNknl4a/RPTUDmXvybBgaOcHSSWbUKVDUQGZ39xFQAoiV4YvTsaeznIotofhNxBz7kDCOEvGdKyBG8g8hTs70L4Pw4QFDPqfWBO53po6M0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=fVk62MPi; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fVk62MPi" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 511F04E4119C; Mon, 10 Aug 2026 07:58:29 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 1040E6033B; Mon, 10 Aug 2026 07:58:29 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EE47C11C49CA4; Mon, 10 Aug 2026 09:58:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1786348704; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=AgtKz8mbEXrrynBzyJW+mHxmZTV0nQNNdf/m3uMU3oM=; b=fVk62MPi/+BWpwsj8e/pI4iiIYIE7W81BsStg9ymkbagMoWXmjTrxTZEiXl8Y/pAMjo1Ja hLOhlyW+wi3i4QsATMYZw4YNmn+vJQj5fUxxfIlnsrJbxAG8BTtrVtd3rwqVXAISwALi4I uhGf6F11a30bOWzstKDwJeeLWFOO0yW+R4cwi8GflHYOLFdAwAQ+lWIPLtD9i72y3xExNX 44TNfAmMvnZgfsfbbKET6Rx8UpmtLzq2Aiz1J3O8O/QDENdDEWxt8eURxG/5l/PFO2MZXj T4XArYNrS7Lsb4FKbmp9XkeLAQ+HLPgjRNcguhhZOOtij8j/QGGGXcTch/0n6Q== From: Miquel Raynal To: han.xu@oss.nxp.com Cc: Richard Weinberger , Vignesh Raghavendra , Peter Pan , Boris Brezillon , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Han Xu Subject: Re: [PATCH] mtd: spinand: Enable QE on all dies In-Reply-To: <20260807-spinand_qe-v1-1-c102c79834a3@nxp.com> (han xu's message of "Fri, 07 Aug 2026 18:11:27 -0500") References: <20260807-spinand_qe-v1-1-c102c79834a3@nxp.com> User-Agent: mu4e 1.12.12; emacs 30.2 Date: Mon, 10 Aug 2026 09:58:20 +0200 Message-ID: <87qzk6s8yr.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Hello Han, On 07/08/2026 at 18:11:27 -05, han.xu@oss.nxp.com wrote: > From: Han Xu > > The QUAD ENABLE (QE) bit is stored in a per-die configuration > register on some SPI-NAND devices. When a device contains multiple > dies, updating the QE bit only on the currently selected die can > leave the remaining dies operating in non-quad mode. > =C2=A0 > Iterate over all targets and update the QE setting on each die > during initialization to ensure consistent quad I/O operation > across the entire device. > > Tested on ISSI IS38SMW04G8B. > > Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support > SPI NANDs") There was no ISSI device back then, but I guess this can be useful for other devices. However this shall be backported, so Cc: stable. > Signed-off-by: Han Xu > --- > drivers/mtd/nand/spi/core.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c > index 35365b67dd8e..744662533f37 100644 > --- a/drivers/mtd/nand/spi/core.c > +++ b/drivers/mtd/nand/spi/core.c > @@ -281,8 +281,26 @@ static int spinand_init_cfg_cache(struct spinand_dev= ice *spinand) > static int spinand_init_quad_enable(struct spinand_device *spinand, > bool enable) > { > - return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, > - enable ? CFG_QUAD_ENABLE : 0); > + struct nand_device *nand =3D spinand_to_nand(spinand); > + unsigned int target; > + int ret; > + > + /* > + * QE is a per-die setting on some devices. Program each target > + * individually when enabling or disabling quad I/O mode. > + */ > + for (target =3D 0; target < nand->memorg.ntargets; target++) { > + ret =3D spinand_select_target(spinand, target); > + if (ret) > + return ret; > + > + ret =3D spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, > + enable ? CFG_QUAD_ENABLE : 0); > + if (ret) > + return ret; If there is an issue in the middle of the loop, the chip will become unusable. Perhaps we should reset the dies to the !QE state and return an error to continue in degraded (single) mode if that happens? Thanks, Miqu=C3=A8l