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From: Thomas Gleixner <tglx@linutronix.de>
To: Marc Zyngier <maz@kernel.org>, Manivannan Sadhasivam <mani@kernel.org>
Cc: Qiang Yu <qiang.yu@oss.qualcomm.com>, linux-kernel@vger.kernel.org
Subject: Re: MSIs not freed in GICv3 ITS driver
Date: Tue, 07 Apr 2026 12:45:51 +0200	[thread overview]
Message-ID: <87qzor59r4.ffs@tglx> (raw)
In-Reply-To: <86zf3m3bps.wl-maz@kernel.org>

On Wed, Apr 01 2026 at 17:08, Marc Zyngier wrote:
> On Wed, 01 Apr 2026 13:01:49 +0100,
> Manivannan Sadhasivam <mani@kernel.org> wrote:
> 1 *IS* a power of two. Any driver that does that is perfectly fine.
>
> A driver that does
>
> pci_alloc_irq_vectors(pdev, 1, 7, PCI_IRQ_MSI);
>
> or
>
> pci_alloc_irq_vectors(pdev, 7, 7, PCI_IRQ_MSI);
>
> is broken. *That* is what the PCI core code should enforce.

No.

The PCI MSI specification mandates that the number of MSI vectors
supported by a device has to be a power of two. That's what the kernel
reads from the 'Multiple Message Capable' field in the MSI control word.

It also mandates the the number of enabled vectors in the 'Multiple
Message Enable' field of the MSI control word is a power of two and has
to be less and equal than the Capable field.

But the specification does not mandate at all how many vectors a driver
uses for operation. It neither mandates that a device can actually
utilize all possible vectors it advertises.

So having a MSI capable device which supports 5 vectors is perfectly
valid. In order to do that, the device must have the Capable field
populated to '8' and PCI core has to write 8 to the Enable field in
order to allocate 5 vectors.  That's the only requirement.

For MSI-X there is no explicit power of two requirement in the
specification at all. The message table size is encoded in the Table
Size field without any power of two requirement. The description of the
Pending Bit Array makes this entirely clear:

 "The Pending Bit Array (PBA) structure, illustrated in Figure 6-4,
  contains the function’s Pending Bits, one per Table entry, organized
  as a packed array of bits within QWORDs.  The last QWORD will not
  necessarily be fully populated."

So it is clearly not something which can be enforced by the PCI core or
imposed on drivers. It's a problem of the underlying infrastructure.

If underlying infrastructure has power of two requirements to
e.g. allocate a redirection table, then it has to ensure that on its own
and not impose restrictions on everybody else for it's own conveniance.

Thanks,

        tglx

  parent reply	other threads:[~2026-04-07 10:45 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-08 15:39 MSIs not freed in GICv3 ITS driver Manivannan Sadhasivam
2024-07-08 17:31 ` Marc Zyngier
2024-07-09 17:37   ` Manivannan Sadhasivam
2024-07-09 19:24     ` Marc Zyngier
2024-07-21  8:50       ` Manivannan Sadhasivam
2026-01-16 15:03         ` Manivannan Sadhasivam
2026-02-19 16:54           ` Marc Zyngier
2026-02-25  9:34             ` Qiang Yu
2026-02-26 13:39               ` Marc Zyngier
2026-03-03  5:22                 ` Qiang Yu
2026-03-03  9:26                 ` Manivannan Sadhasivam
2026-03-30  8:17                   ` Marc Zyngier
2026-04-01  7:59                     ` Manivannan Sadhasivam
2026-04-01  8:15                       ` Marc Zyngier
2026-04-01 12:01                         ` Manivannan Sadhasivam
2026-04-01 16:08                           ` Marc Zyngier
2026-04-01 17:37                             ` Manivannan Sadhasivam
2026-04-07 10:45                             ` Thomas Gleixner [this message]
2026-04-07 12:18                               ` Manivannan Sadhasivam

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