From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6723B3CF046 for ; Thu, 2 Apr 2026 13:46:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775137565; cv=none; b=AIw+EgSQJTl1ifLJULd8s24ivW5AdDXZ69Zz8B7cuB1LMiR1jYEtTS3/Vosf1rH3XwC5BfyWKOouvN2xgAyrrt9N0vHs84ezvbcnNglDELw7qQiBpgxK/HjA9fprdZ/6vURuK47j13JIyD0ZAJFB95LEKT5X9uHNxWW5oFROxio= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775137565; c=relaxed/simple; bh=eG0p04wUimw+QZzsLWCpXTsO6q93OO+vXzTIDXl9VIo=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=uBbatE2QqxlnxMCX2rv5Q9aZ0NUkyAN4IWqxbf0Of/rvQAWOS6lTH5cOaxOAqcyQHUFmzTP6SyTKrdtXT3VCgxvBzTuRkZkR0BD2NpguD0J/KdRwXssaXXgze/f0sq5KlLu3wTlzO1W0HCIylqqbavjWUBusAeBaUnTYNNkT4Yo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=guPH4p3G; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="guPH4p3G" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6DCFEC19424; Thu, 2 Apr 2026 13:46:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775137565; bh=eG0p04wUimw+QZzsLWCpXTsO6q93OO+vXzTIDXl9VIo=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=guPH4p3GBmRaF98CVBBiEBVx7clp3yx3PeXTA0e/2H2DId0MUY7DobgMDdVuH00tk hOt/F2uBYs8FJrYW5nQm4XfKN96XxHTVmkDj+PfIjmaW+u/RCLUfAODgXMXA2lAEx8 bIZ5iHs7IJilaafEl8Kk4qK1gLrffrEmJn2zq+uXklSpIjQuu8VzsCE5Ne28jl1qfe 6axOHMobZELbynodVMcUlJQFkp7IZeHWAF3+FJMgCCvFDza8EP6/p4JXOKBXzaya63 gsfk/VNj2dMrqOra6g5/fTgI+6Mt2lOG+11eY2MvplEKFLT1Is/2MFLIaU7B6OrRHS FG4QNSspAgLHA== From: Thomas Gleixner To: Michael Kelley , LKML Cc: "x86@kernel.org" , Dmitry Ilvokhin , Radu Rendec , Jan Kiszka , Kieran Bingham , Florian Fainelli , Marc Zyngier Subject: RE: [patch V5 00/15] Improve /proc/interrupts further In-Reply-To: References: <20260401195625.213446764@kernel.org> Date: Thu, 02 Apr 2026 15:46:01 +0200 Message-ID: <87qzox79wm.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Thu, Apr 02 2026 at 02:32, Michael Kelley wrote: > From: Thomas Gleixner Sent: Wednesday, April 1, 2026 2:51 PM > The improved alignment looks good. But if you want to be picky > about the alignment, I noticed these things: > > On x86, the leftmost column now correctly aligns the "VPMI:" label. > But the rightmost column does not correctly align the text > "Perf Guest Mediated PMI". It needs one additional space. Here's my > output (with some CPU columns removed so it's not so wide): > > root@mhkubun:~# cat /proc/interrupts | cut -b 1-30,64- > CPU0 CPU1 CPU5 CPU6 CPU7 > 8: 0 0 0 0 0 IO-APIC 8-edge rtc0 > 9: 0 0 0 0 0 IO-APIC 9-fasteoi acpi > NMI: 0 0 0 0 0 Non-maskable interrupts > LOC: 0 0 0 0 0 Local timer interrupts > PMI: 0 0 0 0 0 Performance monitoring interrupts > IWI: 1 0 0 0 0 IRQ work interrupts > RES: 325 231 235 341 231 Rescheduling interrupts > CAL: 11547 7178 9033 8798 6738 Function call interrupts > TLB: 0 0 0 0 0 TLB shootdowns > TRM: 0 0 0 0 0 Thermal event interrupt > THR: 0 0 0 0 0 Threshold APIC interrupts > MCE: 0 0 0 0 0 Machine check exceptions > MCP: 3 3 3 3 3 Machine check polls > HYP: 7300 5185 278 6960 1213 Hypervisor callback interrupts > HRE: 0 0 0 0 0 Hyper-V reenlightenment interrupts > HVS: 8963 4359 9784 8374 61709 Hyper-V stimer0 interrupts > PIN: 0 0 0 0 0 Posted-interrupt notification event > NPI: 0 0 0 0 0 Nested posted-interrupt event > PIW: 0 0 0 0 0 Posted-interrupt wakeup event > VPMI: 0 0 0 0 0 Perf Guest Mediated PMI That's weird. Let me have a look. > On arm64, the leftmost column doesn't align the IPI entries. > Neither does the rightmost column for the IPI entries. Here's some > of my output: > > 45: 0 0 80 0 0 HV-PCI-MSIX-0817:00:02.0 14 Edge mlx5_comp13@pci:0817:00:02.0 > 46: 0 0 0 10 0 HV-PCI-MSIX-0817:00:02.0 15 Edge mlx5_comp14@pci:0817:00:02.0 > 47: 0 0 0 0 45 HV-PCI-MSIX-0817:00:02.0 16 Edge mlx5_comp15@pci:0817:00:02.0 > IPI0: 906 536 649 495 606 Rescheduling interrupts > IPI1: 28844 12457 14770 55242 39175 Function call interrupts > IPI2: 0 0 0 0 0 CPU stop interrupts > IPI3: 0 0 0 0 0 CPU stop NMIs > IPI4: 0 0 0 0 0 Timer broadcast interrupts > IPI5: 11 1 5 0 2 IRQ work interrupts > IPI6: 0 0 0 0 0 CPU backtrace interrupts > IPI7: 0 0 0 0 0 KGDB roundup interrupts > Err: 0 So the problem is that the default width for the interupt number is 3, while the IPI entries need 4. I can I make that default to 4. The text of the IPIs is prepadded in arm64's arch_show_interrupts().