From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E530617C9E; Sun, 4 Aug 2024 11:24:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722770688; cv=none; b=AlkLUr7V2doimVMCsQ79eeycXUWuxkg1WJTo/grB2C+mMLUE8YVN5DxQZvX6xKGSiwDnozFOLRZFuwbvT6zhkCK1Qt9LxGJKTigvpNiiFntY2bYPV9o+iF/Zb9mIsI/URo4wOavrCkqv0JTqNcfWKB4F8/aM7HNQlHwyC6C9g0s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722770688; c=relaxed/simple; bh=jfqjxc5xPJuMgsSjsvqDsL7sb1Gzrg2zNgXmKJd1RW4=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=p1SVRfMgP+jvc8DIwiO6mpf6KIvpe1kfVfNfFunHFYNRKaCJeSZ9SBB2IKDoWVUbT8JS2aNdH73MOqhuPDNe2w5pJnoi8iZ8Gn3sRAEqK10L+mWgqMPjnpypkqvILcuASkw9x/WCRvgW2LqpP452XT0bnWof/JzYO/uvBuEOIys= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hPvnVOiX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hPvnVOiX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70A82C32786; Sun, 4 Aug 2024 11:24:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722770687; bh=jfqjxc5xPJuMgsSjsvqDsL7sb1Gzrg2zNgXmKJd1RW4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=hPvnVOiXthTCqw0/iV56gPy/TMy2T4AkkOp5tsUnNZz6CS5dtk9Yof7AYm/h/Rf2z F7Ra0+Vr9o1lNzSrTqSFIP3DTbPVzw3PHVxtxtWLSTPwPKJtiiDaD7SaobPt/GC0G8 TpA6GnJKe20aSTTbL0ANvK+2pfpPlseoot5T2+uSQ0WEQ8G8OYZB0DkG3d2miXu/tP 1sf8jyRPRRxVrzt2JEeIVDfXelPO9ak4PpkPii/9QOBibN+trHbkB5fiH1w0kxE9Q+ u+F7dpYCmlkib7H+ltxBPtsXNOSMmjJz8ZjEPSE0QfD5CynpDxsiY/DRGpLzjtvilS HaBn3avYTHsNQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1saZLx-000l99-7K; Sun, 04 Aug 2024 12:24:45 +0100 Date: Sun, 04 Aug 2024 12:24:44 +0100 Message-ID: <87r0b44jk3.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Oliver Upton , James Morse , Suzuki K Poulose , Paolo Bonzini , Shuah Khan , Catalin Marinas , Joey Gouly , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] KVM: selftests: arm64: Simplify specification of filtered registers In-Reply-To: <20240802-kvm-arm64-get-reg-list-v1-1-3a5bf8f80765@kernel.org> References: <20240802-kvm-arm64-get-reg-list-v1-0-3a5bf8f80765@kernel.org> <20240802-kvm-arm64-get-reg-list-v1-1-3a5bf8f80765@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, pbonzini@redhat.com, shuah@kernel.org, catalin.marinas@arm.com, joey.gouly@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 02 Aug 2024 22:57:53 +0100, Mark Brown wrote: > > Since we already import the generated sysreg definitions from the main > kernel and reference them in processor.h for use in other KVM tests we > can also make use of them for get-reg-list as well instead of having hard > coded magic numbers in the program. Do this for the table defining which > registers should be gated on ID register values, using a macro which allows > us to specify the register and ID register field in a much more compact > and direct fashion. > > In the process we fix the ID register checked for S1PIE specific registers > which was using an incorrect shift of 4, checking SCTLRX support instead. > No other change is seen in the generated data. > > Fixes: 5f0419a0083b ("KVM: selftests: get-reg-list: add Permission Indirection registers") > Signed-off-by: Mark Brown > --- > tools/testing/selftests/kvm/aarch64/get-reg-list.c | 29 ++++++++-------------- > 1 file changed, 11 insertions(+), 18 deletions(-) > > diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c > index 709d7d721760..a00322970578 100644 > --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c > +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c > @@ -22,25 +22,18 @@ struct feature_id_reg { > __u64 feat_min; > }; > > -static struct feature_id_reg feat_id_regs[] = { > - { > - ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */ > - ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ > - 0, > - 1 > - }, > - { > - ARM64_SYS_REG(3, 0, 10, 2, 2), /* PIRE0_EL1 */ > - ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ > - 4, > - 1 > - }, > - { > - ARM64_SYS_REG(3, 0, 10, 2, 3), /* PIR_EL1 */ > - ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ > - 4, > - 1 > +#define FEAT_ID_CHECK(reg, id_reg, id_field, id_val) \ > + { \ > + KVM_ARM64_SYS_REG(SYS_##reg), \ > + KVM_ARM64_SYS_REG(SYS_##id_reg), \ > + id_reg##_##id_field##_SHIFT, \ > + id_reg##_##id_field##_##id_val, \ Please use designated initialisers. > } > + > +static struct feature_id_reg feat_id_regs[] = { > + FEAT_ID_CHECK(TCR2_EL1, ID_AA64MMFR3_EL1, TCRX, IMP), > + FEAT_ID_CHECK(PIRE0_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), > + FEAT_ID_CHECK(PIR_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), > }; > > bool filter_reg(__u64 reg) Thanks, M. -- Without deviation from the norm, progress is not possible.